1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - drw 07-01-22 Joseph Rodenbeck THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV A SHET 15 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2
2、 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles E. Besore COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT,
3、 LINEAR, MICROPROCESSOR COMPATIBLE, 12-BIT ANALOG-TO-DIGITAL AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-08-30 CONVERTERS, MULTICHIP AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-88615 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E190-07 Provided by IHSNot for ResaleNo rep
4、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compli
5、ant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88615 01 X A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type
6、s. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 AD674AU Multichip, high performance, 12-bit A/D converter with microprocessor interface 02 AD674AT Multichip, high performance, 12-bit A/D converter with microprocessor interface 1.2.2 Case o
7、utlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
8、 1.3 Absolute maximum ratings. VCCto digital common 0 V dc to +16.5 V dc VEEto digital common 0 V dc to -16.5 V dc VLOGICto digital common 0 V dc to +7 V dc Analog common to digital common 1 V dc Control inputs (CE, CS , AO, 12/ 8 , R/ C ) to digital common. -0.5 V dc to VLOGIC+0.5 V dc Analog input
9、s (REF IN, BIP OFF, 10 VIN) to analog common 16.5 V dc 20 VINanalog input voltage to analog common 24 V dc VREF OUTIndefinite short to common 10 ms short to VCCPower dissipation (TA= +25C): 833 mW Lead temperature (soldering, 10 seconds) +300C Storage temperature range -65C to +150C Junction tempera
10、ture (TJ) +175C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA): Case X . +60C/W Case 3 +70C/W 1.4 Recommended operating conditions. Logic supply voltage (VLOGIC) . +4.75 V dc to +5.25 V dc Positive supply voltage (VCC) . +11.4 V dc to +16.5 V
11、 dc Negative supply voltage (VEE) -11.4 V dc to -16.5 V dc Ambient operating temperature range (TA) -55C to +125C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,
12、 OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of
13、these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Elec
14、tronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Sta
15、ndardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, superse
16、des applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing th
17、at is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval
18、 in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or
19、“QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines.
20、 The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, th
21、e electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are describe
22、d in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitation
23、s, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ cer
24、tification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 RE
25、VISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VLOGIC= +5 V, VEE= -15 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Power supply current from VLOGIC2/ ILOGICThree-state
26、 outputs 1, 2, 3 All +45 mA Power supply current from VCC2/ ICC1, 2, 3 All +5 Power supply current from VEE2/ IEE1, 2, 3 All -29 Integral linearity error LE Unipolar 10 V span, Biploar 20 V span 1 All -0.5 +0.5 LSB 2, 3 -1.0 +1.0Differential linearity error (minimum resolution for which no missing c
27、odes are guaranteed) DLE Unipolar 10 V span, Biploar 20 V span 1, 2, 3 All 12 Bits Unipolar offset voltage error VIO10 V span 1 All -2 +2 LSB Unipolar offset voltage drift VIOT 2, 3 All -1 +1Bipolar offset error BZ20 V span 1 All -4 +4 LSB Bipolar offset drift BZT 2, 3 01 -1 +102 -2 +2 Gain error AE
28、With 50 resistor from REF OUT to REF IN, Bipolar 20 V span, TA= +25C 1 All -0.25 +0.25 % of FS Gain error AET Bipolar 20 V span 2, 3 01 12.5 ppm/C 02 25 Power supply sensitivity to VCC3/ 4/ +PSS1 Unipolar 10 V span 1, 2, 3 All -1 +1 LSB Power supply sensitivity to VCC3/ 5/ +PSS2 Unipolar 10 V span 1
29、, 2, 3 All -0.5 +0.5 LSB Power supply sensitivity to VCC3/ 6/ -PSS3 Unipolar 10 V span 1, 2, 3 All -1 +1 LSB Input impedance 2/ ZIN10 V span 1, 2, 3 All 3 7 k 20 V span 6 14 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
30、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VLOGIC= +5 V, VEE= -15 V Group A
31、 subgroups Device type Limits Unit unless otherwise specified Min Max Internal reference voltage 7/ VREFBipolar 20 V span, IREFOUT= 2 mA 1, 2, 3 All +9.9 +10.1 V Logic input high voltage (CE, CS , 12/ 8, R/C, AO) 2/ 8/ VIHLogic “1” 1, 2, 3 All +2.0 V Logic input low voltage (CE, CS , 12/ 8, R/C, AO)
32、 2/ 8/ VILLogic “0” 1, 2, 3 All +0.8 V Logic input current 2/ IIN(LOG)VIH= 5.0 V, VIL= 0.0 V 1, 2, 3 All -100 +100 A Logic low output voltage (DB11-DB0, STS) 2/ VOLLogic “0”, ISINK= +1.6 mA 1, 2, 3 All +0.4 V Logic high output voltage (DB11-DB0, STS) 2/ VOHLogic “1”, ISOURCE= 500 A 1, 2, 3 All +2.4
33、V Three-state output leakage current (DB11-DB0) IOLTHigh-Z state, VAPPLIED= 5.0 V 1, 2, 3 All -20 +20 A Functional tests 2/ (See 4.3.1c) 7, 8 All Low R/ C pulse width 9/ tHRLSee figure 3 9, 10, 11 All 50 ns STS delay from R/ C 10/ tDS200 Data valid after R/ C low 11/ tHDR25 STS delay after valid dat
34、a tHS 30 600 High R/ C pulse width 9/ tHRH150 Data access time 12/ tDDR150 STS delay from CE 10/ tDSCSee figure 4 9, 10, 11 All 200 ns CE pulse width 9/ tHEC50 CS to CE setup tSSC50 CS low during CE high tHSC50 R/ C to CE setup tSRC50 R/ C low during CE high tHRC50 See footnotes at end of table. Pro
35、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - con
36、tinued. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VLOGIC= +5 V, VEE= -15 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max AOto CE setup tSACSee figure 4 9, 10, 11 All 0 ns AOvalid during CE high tHAC50 Conversion time 13/ tC8-bit cycle, see figure 4 9, 10, 11
37、All 6 10 s 12-bit cycle, see figure 4 9 15 Access time (from CE) 12/ tDDSee figure 5 9, 10, 11 All 150 ns Data valid after CE low 11/ tHD25 Output float delay 11/ tHL150 CS to CE setup tSSR50 R/ C to CE setup tSRR0 AOto CE setup tSAR50 CS valid after CE low tHSR0 R/ C high after CE low tHRR0 AOvalid
38、 after CE low tHAR50 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 9
39、7 TABLE I. Electrical performance characteristics - continued. 1/ 12/ 8 connected to VLOGIC, AOand CS at logic “0”, CE at logic”1”. 10 V unipolar: 50 resistor pin 8 to pin 10, 50 resistor pin 12 to ground. Analog input connected to pin 13. 20 V bipolar: 50 resistor pin 8 to pin 12, 50 resistor pin 8
40、 to 10. Analog input connected to pin 14. These conditions apply unless otherwise noted. 2/ Device types are tested to the conditions stated in table I, but are guaranteed to the specified limits for the following variations in the supply voltage ranges. VLOGIC= 5 V to 5%, VCC= +12 V 5% and +15 V to
41、 10%, VEE= -12 V 5% and -15 V to 10%. 3/ Maximum change in full scale calibration due to supply voltage shifts. Full scale calibration to be measured at minimum and maximum voltage settings for each individual supply. 4/ +13.5 V VCC +16.5 V, VLOGIC= 5 V, VEE= -15 V and +11.4 V VCC +12.6 V, VLOGIC= 5
42、 V, VEE= -12 V. 5/ 4.75 V VLOGIC 5.25 V, VCC= 15 V, VEE= -15 V. 6/ -16.5 V VEE -13.5 V, VLOGIC= 5 V, VCC= +15 V and -12.6 V VEE -11.4 V, VLOGIC= 5 V, VCC= +12 V. 7/ Reference should be buffered for operation on 12 V supplies. External load should not change during conversion. 8/ 12/ 8 is not TTL com
43、patible and must be hard-wired to VLOGICor digital common. 9/ Pulse width is measured at the Schottky TTL input logic threshold voltage (1.3 V). 10/ tDSand tDSCare measured from the point when the input signal crosses the Schottky TTL logic threshold voltage (1.3 V) to when the STS output reaches 2.
44、4 V. No external loading is applied to STS. 11/ tHDR, tHDand tHLare measured from the point when the input signal crosses the Schottky TTL logic threshold voltage (1.3 V) to when the output voltage has moved 0.5 V in the direction of its final high impedance output voltage. Each individual data bit
45、(DB0 DB11) is measured for both logic “1” to “high Z” and logic “0” to “high Z” transitions. External loading is as shown on figure 7. 12/ tDDRand tDDare measured from the point when the input signal crosses the Schottky TTL logic threshold voltage (1.3 V) to when the output crosses either 2.4 V for
46、 a logic “1”, or 0.4 V for a logic “0”. Each individual data bit (DB0 DB11) is measured for both “high Z” to logic “0” transitions. External loading is as shown on figure 7. 13/ tCis measured as the time from when the STS line crosses the 1.0 V level, going positive, to when it crosses the 1.0 V lev
47、el going negative. No external loading is applied to STS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234
48、 APR 97 Device types 01 and 02 Case outlines X and 3 Terminal number Terminal symbol 1 +5 V supply (VLOGIC) 2 Data mode select (12/ 8) 3 Chip select ( CS ) 4 Byte address/short cycle (AO) 5 Read/convert (R/ C) 6 Chip enable (CE) 7 +12 V/+15 V supply (VCC) 8 +10 V reference (REF OUT) 9 Analog common (AGND) 10 Reference input (REF IN) 11 -12 V/-15 V supply (VEE) 12 Bipolar offset (BIP OFF) 13 10 V span input (10 VIN) 14 20 V span input (20 VIN) 15 Digital common (DGND) 16 DB0 (LSB)
