1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 02. Add a new case outline to 1.2.2. Technical changes to 1.3 and 1.4. Technical changes to table I. Clarification made on figure 3. Add vendor CAGE code 01295. Editorial changes throughout. 91-08-29 D. M. Cool B Changes in accord
2、ance with NOR 5962-R042-94. 93-11-18 M. L. Poelking C Add device type 03. Update boilerplate. Editorial changes throughout. 95-07-06 T. M. Hess D Changes in accordance with NOR 5962-R004-00. 00-01-31 Monica L. Poelking E Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-03-22 Thomas M. Hess
3、 F Update boilerplate to MIL-PRF-38535 requirements. - PHN 13-05-06 Thomas M. Hess REV SHEET REV F F F F F F F F F F SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Tim H. Noh DLA LAND AND MARITIME C
4、OLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Tim H. Noh THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY D. M. Cool MICROCIRCUIT, DIGITAL, CMOS, SIGNAL AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-08-16 PROC
5、ESSOR, MONOLITHIC SILICON AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-88619 F SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E356-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88619 DLA LAND AND MARITI
6、ME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete P
7、IN is as shown in the following example: 5962-88619 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 320C25 Digital signal p
8、rocessor, 40 MHz 02 320C25-50 Digital signal processor, 50 MHz 03 320C26B Digital signal processor, 40 MHz 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA15-P68 68 Pin grid array Y CQCC1
9、-N68 68 Square leadless chip carrier Z CQCC2-J68 68 “J” lead chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range (VCC) -0.3 V dc to +7.0 V dc 1/ Input voltage range (VI) -0.3 V dc to +7.0 V dc Output voltage
10、 range (VO) -0.3 V dc to +7.0 V dc Continuous total power dissipation (PD) . 1.0 W Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) . +150C _ 1/ Voltage values for maximum r
11、atings are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88619 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating c
12、onditions. Supply voltage range (VCC): Device types 01 and 03 4.5 V dc to 5.5 V dc Device type 02 4.75 V dc to 5.25 V dc Supply voltage (VSS) . 0 V dc High level output current (IOH) 300 A Low level output current (IOL) . 2 mA High level input voltage (VIH): D15-0 2.20 V dc minimum FSX device type 0
13、1 . 2.30 V dc minimum FSX device types 02, 03 . 2.20 V dc minimum CLKR/CLKX 3.50 V dc minimum CLKIN: Device type 01 and 03 . 3.50 V dc minimum Device type 02 . 4.00 V dc minimum All others . 3.00 V dc minimum Low level input voltage (VIL): D15-0/FSX/CLKIN/CLKX/CLKR 0.8 V dc maximum All others . 0.7
14、V dc maximum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues
15、of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard E
16、lectronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the
17、Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supe
18、rsedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88619 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHE
19、ET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML)
20、 certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as docu
21、mented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-3853
22、5 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2
23、 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Functional block diagrams. The functional block diagrams shall be as specified on figure 2. 3.2.4 Timing waveforms and test circuits. The timing waveforms and test circuits shall be as specified on
24、 figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be
25、 the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For pa
26、ckages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-
27、38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be list
28、ed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requireme
29、nts herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any chan
30、ge that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the opti
31、on of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88619 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance charact
32、eristics. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage VOHVCC= 4.5 V dc, IOH= -300 A VIN= VILmax, VIHmin 1, 2, 3 01, 03 2.4 V VCC= 4.75 V dc, IOH= -300 A 02 Low level output voltage VOLVCC= 4.5 V dc, IOL=
33、2 mA VIN= VILmax, VIHmin 1, 2, 3 01, 03 0.6 V VCC= 4.75 V dc, IOL= 2 mA 02 Three-state current IZVCC= 5.5 V dc VIN= 0 V 1, 2, 3 01, 03 -20 A VIN= VCC20 VCC= 5.25 V dc VIN= VCC02 -20 VIN= 0 V 20 Input current (X2/CLKIN) IIVI= VCCVCC= 5.5 V 1, 2, 3 01 20 A VCC= 5.25 V 02 20 VCC= 5.5 V 03 10 VI= VSSVCC
34、= 5.5 V 01 -20 VCC= 5.25 V 02 -20 VCC= 5.5 V 03 -10 Input current (All others) IIVI= VCCVCC= 5.5 V 1, 2, 3 01 10 A VCC= 5.25 V 02 10 VCC= 5.5 V 03 10 VI= VSSVCC= 5.5 V 01 -10 VCC= 5.25 V 02 -10 VCC= 5.5 V 03 -10 Supply current ICCNormal VCC= 5.5 V dc, fX= 40 MHz 1, 2, 3 01, 03 185 mA Idle/Hold 100 N
35、ormal VCC= 5.25 V dc, fX= 50 MHz 02 185 Idle/Hold 100 Input capacitance CINVIN= 100 mV, TC= +25C, Freq = 1 MHz, VCC= 0.0 V See 4.3.1c 4 All 15 pF Output capacitance COUT4 All 20 pF Bidirectional capacitance CI/O4 All 20 pF Functional tests VCC= min, max See 4.3.1d 7, 8 All See footnotes at end of ta
36、ble. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88619 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Cont
37、inued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Internal clock option Input clock frequency fXSee figure 3. 1/ 2/ 4/ 9, 10, 11 01, 03 6.7 40 MHz 02 6.7 50 External clock option CLKOUT1/CLKOUT2 cycle time tC(C)See figure 3. 3/ 4
38、/ 9, 10, 11 01, 03 100 600 ns 02 80 600 CLKIN high to CLKOUT1, CLKOUT2, STRB high/low td(CIH-C)9, 10, 11 01 5 30 ns 02 5 28 03 5 32 CLKOUT1/CLKOUT2 STRB fall time 2/ tf(C)9, 10, 11 01, 03 5 ns 02 3 CLKOUT1/CLKOUT2 STRB rise time tr(C)9, 10, 11 01, 03 5 ns 02 3 CLKOUT1/CLKOUT2 low pulse duration tw(C
39、L)9, 10, 11 01, 03 2Q-8 2Q+8 ns 02 2Q-7 2Q+5 CLKOUT1/CLKOUT2 high pulse duration tw(CH)9, 10, 11 01, 03 2Q-8 2Q+8 ns 02 2Q-1 2Q+7 CLKOUT1( high or low) to CLKOUT2 (high or low) td(C1-C2)9, 10, 11 01, 03 Q-6 Q+6 ns 02 Q-6 Q+3 CLKIN cycle time tc(CI)9, 10, 11 01, 03 25 150 ns 02 20 150 CLKIN low pulse
40、 duration 5/ tw(CIL)tc(CI)= 25 ns See figure 3. 3/ 4/ 9, 10, 11 01, 03 10 15 ns 02 8 CLKIN high pulse duration 5/ tw(CIH)9, 10, 11 01, 03 10 15 ns 02 8 SYNC setup time before CLKIN low tsu(S)See figure 3. 3/ 4/ 9, 10, 11 01, 03 5 Q-5 ns 02 4 Q-4 SYNC hold time from CLKIN low th(S)9, 10, 11 01, 03 8
41、ns 02 4 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88619 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical
42、performance characteristics - Continued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Memory and peripheral interface timing STRB from CLKOUT1 (if STRB is present) td(C1-S)See figure 3. 3/ 4/ 9, 10, 11 01, 03 Q-6 Q+6 ns 02 Q-5 Q+3
43、CLKOUT2 to STRB (if STRB is present) td(C2-S)9, 10, 11 01, 03 -6 6 ns 02 -2 5 Address setup time before STRB low 6/ tsu(A)9, 10, 11 01, 03 Q-12 ns 02 Q-13 Address hold time after STRB high 6/ tsu(A)9, 10, 11 01, 03 Q-8 ns 02 Q-4 STRB low pulse duration (no wait states) 7/ tw(SL)9, 10, 11 01, 03 2Q-5
44、 2Q+5 ns 02 2Q-5 2Q+3 STRB high pulse duration (between consecutive cycles) 7/ tw(SH)9, 10, 11 01, 03 2Q-5 2Q+5 ns 02 2Q-5 2Q+5 Data write setup time before STRB high (no wait states) tsu(D)W9, 10, 11 01, 03 2Q-20 ns 02 2Q-17 Data write hold time from STRB high th(D)W9, 10, 11 01, 03 Q-10 ns 02 Q-5
45、Data bus starts being driven after STRB low (write cycle) ten(D)1/ 9, 10, 11 All 0 ns Data bus three-state after STRB high (write cycle) tdis(D)2/ 9, 10, 11 All Q+15 ns MSC valid from CLKOUT1 td(MSC)1/ 9, 10, 11 01, 03 -10 10 ns 02 -5 10 Read data access time from address time (read cycle) 6/ 8/ ta(
46、A)9, 10, 11 01, 03 3Q-40 ns 02 3Q-31 Data read setup time before STRB high tsu(D)R9, 10, 11 01, 03 23 ns 02 17 Data read hold time from STRB high th(D)R9, 10, 11 All 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
47、STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88619 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Li
48、mits Unit Min Max Memory and peripheral interface timing - Continued. READY valid after STRB low (no wait states) td(SL-R)See figure 3. 3/ 4/ 9, 10, 11 01, 02 Q-20 ns 03 Q-22 READY valid after CLKOUT2 high td(C2H-R)2/ 9, 10, 11 01 Q-20 ns 02 Q-21 03 Q-22 READY hold time after STRB low (no wait states) th(SL-R)9, 10, 11 01, 03 Q+3 ns 02 Q-1 READY hold after CLKOUT2 high th(C2H-R)1/ 9, 10, 11 01, 03 Q+3 ns 02 Q-1 READY valid after MSC valid td(M-R)2/ 9, 10, 11 All 2Q-25 ns READY hold time after MSC valid th(M-R)1/ 9, 10, 11 All 0 ns RS, INT, BIO, and XF timing 9/
