1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change to vendor similar part number. Change to table I. Removed programming procedures for method A, programming waveforms, table III, and ESDS from the drawing. Removed final electrical test from table II. Added device type 04. Editorial change
2、s throughout. 90-02-26 M. A. Frye B Changes in accordance with NOR 5962-R059-96. 96-03-13 M. A. Frye C Update drawing to current requirements. Editorial changes throughout. - gap 01-11-05 Raymond Monnin D Boilerplate update, part of 5 year review. ksr 07-04-02 Robert M. Heber REV SHET REV SHET REV S
3、TATUS REV D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS
4、 APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-09-09 MICROCIRCUIT, DIGITAL, MEMORY, CMOS UV ERASABLE, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-88724 AMSC N/A REVISION LEVEL D SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E31
5、0-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes de
6、vice requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88724 01 K A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2)
7、 Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function tPD01 C22V10L 22-input 10-output 25 ns AND-OR-logic array 02 C22V10L 22-input 10-output 30 ns AND-OR-logic array 03 C22V10L 22-input 10-output 40 ns A
8、ND-OR-logic array 04 C22V10L 22-input 10-output 20 ns AND-OR-logic array 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat package 1/ L GDIP3-T24 or CDIP4-T24 24
9、Dual-in-line 1/ 3 CQCC1-N28 28 Leadless chip carrier 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 2/ Supply voltage range . -0.5 V dc to +7.0 V dc Input voltage range . -2.0 V dc to +7.0 V dc 3/ Output voltage applied -0.5 V dc to
10、+7.0 V dc 3/ Output sink current 16 mA Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Maximum power dissipation (PD) 4/ 1.2 W Maximum junction temperature . +175C Lead temperature (soldering, 10 seconds maximum) . +300C _ 1/ Lid shall be transparent to permit ultraviolet light erasure. 2
11、/ All voltages referenced to VSS. 3/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 4/ Must withstand the added PDdue to short circuit test; e.g.
12、, IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Suppl
13、y voltage range (VCC) . 4.5 V dc to 5.5 V dc High level input voltage (VIH) . 2.0 V dc minimum Low level input voltage (VIL) 0.8 V dc maximum Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specificatio
14、n, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specifica
15、tion for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Cop
16、ies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of t
17、his drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in acc
18、ordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF
19、-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications
20、shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The
21、 design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.2.1 Unprogrammed devices. Th
22、e truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in group A, B, or C inspections (see 4.3), the devices shall be programmed by the manufacturer prior to test with a minimum of 50 percent of the total number of gat
23、es programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.2.2 Programmed devices. The requirements for supplying programmed devices are not part of this drawing. 3.2.3 Logic diagram. The logic diagram shall be as specified on
24、 figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.2.4 Case outlines. The case outlines
25、shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electr
26、ical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers
27、 PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices
28、built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a m
29、anufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and
30、the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change th
31、at affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EPLD
32、S. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EPLDS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.10.2 Programmability of EPLDS. When
33、 specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5. 3.10.3 Verification of erasure of programmability of EPLDS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, ver
34、ification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. Provided by IHSNot for ResaleNo reproduction or networkin
35、g permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ VSS= 0 V, 4.5 V VCC 5.5 V -55C T
36、C +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max High level output VOHIO= -2.0 mA 1, 2, 3 All 2.4 V voltage Low level output VOLIO= 12.0 mA 1, 2, 3 All 0.5 V voltage High impedance output IOZVCC= 5.5 V and 1, 2, 3 All -10 10 A leakage current 2/ VO= 5.5 V, VO= GND
37、 High level input IIHVIH= 5.5 V 1, 2, 3 All 10 A current VIH= 2.4 V 1, 2, 3 All 10 A Low level input current IILVIL= 0.4 V 1, 2, 3 All -10 A IL= GND 1, 2, 3 All -10 A Supply current ICCVCC= 5.5 V 1, 2, 3 All 15 mA Output short circuit IOSVCC= 5.5 V 1, 2, 3 All -30 -90 mA current 3/ Input capacitance
38、 CIVI= 0 V, VCC= 5.0 V 4 All 10 pF 4/ 5/ TA= +25C, f = 1 MHz (see 4.3.1c) Output capacitance COVI= 0 V, VCC= 5.0 V 4 All 12 pF 4/ 5/ TA= +25C, f = 1 MHz (see 4.3.1c) Input or feedback to tPDVCC= 4.5 V, CL= 50 pF 9, 10, 11 01 25 nonregistered output See figure 4, circuit B and 02 30 figure 5 03 40 04
39、 20 ns Clock to output tCO9, 10, 11 01 15 ns 02 20 03 25 04 15 Input to output enable tEAVCC= 4.5 V, CL= 5 pF 9, 10, 11 01 25 ns See figure 4, circuit A and 02 30 figure 5 03 40 04 20 Input to output disable tER9, 10, 11 01 25 ns 02 30 03 40 04 20 See footnotes at end of table. Provided by IHSNot fo
40、r ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbo
41、l Conditions 1/ VSS= 0 V, 4.5 V VCC 5.5 V -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Clock pulse width tWVCC= 4.5 V, CL= 50 pF 9, 10, 11 01 15 ns 4/ 6/ See figure 4, circuit B and 02 20 figure 5 03 27 04 12 Clock period tP9, 10, 11 01 33 ns 02 40 03 55
42、 04 25 Setup time 4/ 6/ tS9, 10, 11 01 18 ns 02 20 03 30 04 17 Hold time 4/ 6/ tH9, 10, 11 All 0 ns Maximum clock frequency fMAX9, 10, 11 01 30 MHz 4/ 6/ 02 25 03 18 04 40 Asynchronous reset tAW9, 10, 11 01 25 ns pulse width 02 30 03 40 04 20 Asynchronous reset tAR9, 10, 11 01 25 ns recovery time 02
43、 30 03 40 04 20 Asynchronous reset to tAP9, 10, 11 01 25 ns registered output 02 30 reset 03 40 04 22 1/ All voltages are referenced to ground. 2/ I/O terminal leakage is the worst case of IIXor IOZ. 3/ Only one output shorted at a time. 4/ Tested initially and after any design or process changes th
44、at affect that parameter, and therefore shall be guaranteed to the limits specified in table I. 5/ All pins not being tested are to be open. 6/ Test applies only to registered outputs. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIR
45、CUIT DRAWING SIZE A 5962-88724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Device types 01 through 04 Case outlines L and K 3 Terminal Terminal symbol number 1 CK/I NC 2 I CK/I 3 I I 4 I I 5 I I 6 I I 7 I I 8 I NC 9 I I 10 I I 11 I I 12 GND
46、 I 13 I I 14 I/O GND 15 I/O NC 16 I/O I 17 I/O I/O 18 I/O I/O 19 I/O I/O 20 I/O I/O 21 I/O I/O 22 I/O NC 23 I/O I/O 24 VCCI/O 25 - I/O 26 - I/O 27 - I/O 28 - VCCFIGURE 1. Terminal connections. Truth table Input pins Output pins CK/I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O X X X
47、 X X X X X X X X X Z Z Z Z Z Z Z Z Z Z NOTES: 1. Z = Three-state 2. X = Dont care FIGURE 2. Truth table (unprogrammed). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88724 DEFENSE SUPPLY CENTER COLUMBUS COL
48、UMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 S1 S0 Output configuration 0 0 Registered/active low 0 1 Registered/active high 1 0 Combinatorial/active low 1 1 Combinatorial/active high 0 = Unblown fuse 1 = Blown fuse FIGURE 3. Logic diagram (unprogrammed). Provided by IHSNot for ResaleNo reproduction or networking permitted without license
