1、DEFENSE LOGISTICS AGENCY DEFENSE ELECTRONICS SUPPLY CENTER 1507 WILMINGTON PIKE DAYTON, OH 45444-5765 IN REPLY REFERTO: DESC-ELDC (Mr. Hess/ (AV 986) 513-296-8526/tmh) JAN 12 i996 SUBJECT: Notice of Revision (NOR) 5962-R021-96 for Standard Microcircuit Drawing (SMD) 5962-89512. Military/Industry Dis
2、tribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD-100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SM. After completion, the NOR should be attached to the subject SMD for future r
3、eference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DESC a certificate of compliance. This is evidenced by an existing active current certificate of compliance on file at DESC alon
4、g with a DESC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DESC is otherwise notified. If you have comments or questions, please contact Tom Hess at (AV)986- 8526 / (513) 296-8526. 1 Encl GONICA L. POELKING Chie
5、f, Custom Microelectronics Branch Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-895L2 REV D m 9999996 0084894 bo4 1. DATE (YYmW) 95-12-18 NOTICE OF REVISION (NOR) This revision described below has been authorized for the document listed. F
6、orm Approved OM8 NO. 0704-0188 2. PR UR G ACPFVIN NO 0.4 0.45 3. WOAAC I V V b. ADDRESS (Street, City, State, Zip Code) 6. NOR NO. 7. CAGE CODE 8. DOCUMENT NO. 67268 5962-89512 4. ORIGINATOR a. TYPED NAME (First, Middle Initial, Defense Electronics Supply Center 1507 Wilmington Pike Dayton, OH 45444
7、-5765 Last) htput low voltage RD, R lutput low voltage RD, WR 11. ECP NO. 10. REVISION LETTER 9. TITLE OF DOCUMENT YONOLITHIC SIL ICON YI CROCIRCUIT, DIGITAL , CMOS, 56-BIT DIGITAL SI GNAL PROCESSOR, vcc = ;:g p ;cc = YC add “D“. Revisions description column: add “Changes in accordance with NOR 5962
8、-R021-96“. Revisions date column: add “95-12-18“. Revision level block: add “D“. Rev status of sheets; For sheets 1, 6, add “O“. Sheet 6. Delete VOL test and replace as follows: ). ACTIVITY AUTHORIZED TO APPROVE CHANGE FOR GOVERNMENT DESC-ELDC Conditions I I Test c. TYPED NAME (First, Middle Initial
9、, Last) Monica L. Poelking htput low voltage Except HREQ, RO, WR I. TITLE .5a. ACTIVITY ACCOMPLISHING REVISION :bief, Custom Microelectronics Branch OESC-ELDC f. DATE SIGNED e. SIGNATURE b. REVISION COMPLETED (Signature) Monica L. Poelking 95-12-18 c. DATE SIGNED Thomas M. Hess 95-12-18 1-1 Change r
10、evision level status to “D“ Group A Subgroups 1. 2, 3 3 Dev i ce Al 1 Al 1 Al 1 Limits Units Min I max I 0.4 IV DD Form 1695, APR 92 Previous editions are obsolete Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-LTR A B C THE ORIGINAT_I REVISION LEVE
11、L C REV C SIZE CAGE 03DE 5 9 62-8 9 512 A 67268 SHEET 1 OF 48 E 99 99996 O0 bLb44 Table I: oorrect limite, figure I: Correct case outline. Editorial changes throughout. changes in accordance with NOR 5962-RO98-93 Add device 02. =torial changes throughout. FIRST PAGE OF THIS HAS BEEN 7Y9 DATE (YR-MO-
12、DA) 92-02-2 1 93-03-10 94-04-25 Monica L. mlking Monica L. mlking Monica L. -ucing I PMTC N/A PREPARED BY Christooher A. Rauch I PANDARDIZED MILITARY DRAWING I THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE I AMSC N/A I I DEFENSE-=SUPPLY- I UAYIVIY, Um
13、Lu 43444 CHECKED BY Tim U. Unh I . . . . . - -. . MICROCIRCUIT, DIGITAL, CMOS, 56-BIT DIGITAL SIGNAL APPROVED BY William Y. Weckman DESC FORM 193 JUL 91 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-E472-93 Provided by IHSNot for ResaleNo reproduction or netw
14、orking permitted without license from IHS-,-,-1 SMD-5762-89512 REV C 9999996 0063645 685 H I - 1/ Must withstand the added PD due to short circuit test; e.g., Ias. 2/ VIL 5 0.2 V dc, VIM 2 Vcc - 2.0 V dc. 3J In order to obtain these results ali inpits must be terminated, i.e., not allowed to float.
15、No dc loads. EXTAL is driven by a square wave. SIZE 5962-89512 STANDARD1 ZED DEFENSE ELECTRONICS SUPPLY CENTER AYIION, OHIO 45444 MILITARY DRAWING A REVISION LEVEL SHEET 2 t C I 1. SCOPE I I 1.1 Scope. This drawing describes device requirements for class 6 microcircuits in accordance uith 1.2.1 of M
16、IL-STD-883, *Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“. 1.2 Part or Identifying Nunber (PINL. The conplete PIN shall be as shown in the following exa o I I I I I Delay from UR assertion to 21b I I II Delay from general purpose I 22a output valid to interrup
17、t I request deassertion for level sensitive fast interryits, If second I interrupt instruction is 1 single cycle I 1 output valid to interrupt I I request deassertion for I I level sensitive fast I I interrupts, if second 1 I interrupt instruction is I I Delay from general purpose I 22b I two cycles
18、 I See footnotes at end of table. Group A ,ubgroups 9,10,11 Device Al 1 Lim Min tC Max 5T+2T *US- 44 - GT+2T *US - GO 4T - 40 3T+2T *WS - 40 - r -60 - 51 -60 - Unit - ns - DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SHD-5962
19、-89512 REV C U 9999996 0061652 815 U TABLE 1. Electrical performance characteristics - Continued. of external clock Synchronous interrupt delay time from the synchronous rising edge of the external clock to the Test 24 1 I s-1 I I STANDARD1 ZED SIZE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENT
20、ER DAYTON, OHIO 45444 REVISION LEVEL 5962-89512 SHEET Delay from IRQA assertion I 26b to fetch of first I interrupt instruction 1 I I of first interrupt I Duration of level sensitive 27a IRPA assertion to fetch 1 instruction Duration of level sensitive I 27b I IRPA assertion to fetch i IRPA assertio
21、n to fetch of first interrupt instruction Delay from level sensitive 28a of first interrupt instruction I of first interrupt I Delay from level sensitive I 28b IRQA assertion to fetch I instruction C I 9 I Conditions I/ I Group A -55C 5 TC-S +125OC Isubgroups I Device unless otherwise specified 1 I
22、I I See figure 4, synchronous interrupt from uait state 1 timing ! I I Vcc = Vcc min I I I I I Vcc = Vcc min, I stop state using IRQA I Stable external clock I stop state using IRQA I See figure 4, recovery from I Vcc = Vcc min, OMR bit 6 = O see figure 4, recovery from I I = Vc min, WR bit 6 = 1 “E
23、ternaF crystal osci 1 Lator Externaf clock I Vfkternaf clock I Externa! clock I kerne? clock I clock, see figure 4, recovery from stop state using IRPA - Vcc = Vc min, DHR bit 6 = O I see figure 4, recovery from I stop state and using IRPA 1 interrupt service t = Vc min, DHR bit 6 = 1 I see figure 4
24、, recovery from I stop state and using IRQA I interrupt service t Vcc = Vc min, OMR bit 6 = O I see figure 4, recovery from I stop state and using IRQA I interrupt service 1 V = Vc min, OnR bit 6 = 1 I I I see figure 4, recovery from stop state and using IRQA interrupt service I L Unit I I I I l I I
25、 I I I I a l I Limits Min 1 Max I A 25 127-10 I ns 191+8 I 19T+30 I i i I I I I 27T+8 127T+30 I - 7/ i i I I I l I I I 128000T I +17T I I - 1310901 I I 19T+8 119T+30 L 25 I I t I I I -l- 34T 1 I 1500001 I 128000T i i +17T I 131067T I I I ubgroups I Device I Min I Max 1 l I I I i i I20 1 I I I I I I
26、I l I I 31 113T+ 1 (4T*WS 1 l+20 5962-89512 REVISION LEVEL SHEET STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SND-5962-89532 REV C O 9999996
27、0063662 7b4 = TABLE I. Electrical performance characteristics - Continued. I I Address valid to UR I 120a assertion. US-O I See figure 4, externat bus timing Group A ;ubg r oups deassertion. US=O 9,10,11 STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Device 5962-
28、89512 SIZE A REVISION LEVEL SHEET C 19 o1 o2 o1 02 Al 1 o1 o2 o1 02 Al I 1 Unit I I I Limits Min I Max I A - “s 1-9 I T I T-9 i T+5 1 21-9 I 21 I T 21-9 I I 1 1 I I (Z*US j i +l)*T 1 I -9 I I I T-12 1 I - l I A I I l T-9 I T+10 I 0 110 I T-9 I T+7 I 1)*T-9 1 1 2T*US I I +T-5 I 1 l I 1-9 I I I I I 3T
29、-8 I Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 SIZE 5962-89512 A REVISION LEVEL SHEET Test Conditions I/ -55C 5 lC.5 +125C s-1 I I I unless otherwise specified
30、I l I I I 2 I (2*US I TI I I I I l (2*US I I I I 2 I I I _I I 1 I I I I I I I I I L its 1 Unit Max I 31-18 I ns +3)*1 I -18 1 T+5 1 21-14 I +2)*T I -14 1 I Group A subgroups L Hin Device Address valid to input data valid. US=O 9,10,11 See figure 4, external 130a i bus timing IV, = vcc min I 130b I -
31、+ 131 I 1 I I I 132a 1 I 133 I I Ai 1 o1 o2 Al 1 Address valid to input data valid. USO Address valid RD assertion T -9 - 1-9 7L RD assertion to input data valid. WS=O RD assertion to input data valid. U90 UR deassertion to RD assert ion 21-15 RD deassertion to RD assert i on i I I I I 134 I 135a i
32、21-10 2T-15 UR deassertion to UR assertion. us=O I 135b I I I I I 136a I 136b I 37-15 UR deassert ion to. UR assertion. WSO RD deassertion to UR assertion. W=O 21-10 RD deassertion to UR assertion. SO 31-10 I See footnotes at end of table. DECC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reprod
33、uction or networking permitted without license from IHS-,-,-SMD-5962-895L2 REV C B 9999996 0061664 537 TABLE I. Electrical Derformance characteristics - Continued. STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, 0810 45444 I Test Is-1 I Conditions I/ I Group A I I -55C S TC
34、5 +125“C Isubgroups I I unless otherwise specified 1 SI 2E 5962-89512 A REVISION LEVEL SHEET :LK low Transition to I 140 IV, =.Vcc min 1 9,10,11 address valid I ISee figure 4 I I t I I l I :LK high transition to UR* I 141 I us = o I USO I ELK high transition to UR* I 142 1 )eassertion I I I 1 I I I
35、assert ion I I CLK high transition RD* I 143 I I 1 I I CLK high transition to RD* 1 144 1 deassertion l I I CLK iou transition to data- out -va 1 id l 45 I I I I CLK Lou transition to date-out-invalid I Deta-In Valid to CLK high I 147 I transition (Setup) I I I I CLK high transition to I 48 I det a-
36、 i nva 1 id (Ho Id) I I I l I CLK Low to address invalid I 149 I See footnotes at end of table. Devi ce 02 Limits 1 Unit Min I Max 1 I I i i 3 I171 a I I I a -I 25 I I l 51 - I I I I I o j -1 I A 1 C 1 21 DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted with
37、out license from IHS-,-,-7 SMD-5962-89512 REV C E4 9999996 O061665 473 STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 See footnotes at end of table. SIZE 5962-89512 A REVISION LEVEL SHEET Group A wbgroups 9,10,11 Devi ce 02 Unit I Limits Min I Max I 1 I A I I a I
38、 I I I 8 I -I I I I I 5 1261 I I u O 21-15 i i l I I I I I I 21(US 14T-15 I -1)2T i-;*ws i 3T 15T+23 I I I I I T-7 I - I I I I l 1-10 I - I I I I I l6 I -I DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical perf
39、ormance characteristics - Continued. NOTES: STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 lhe following pins are active low: RESET, IRQA, IRQB, RD, UR, HEN, HACK, U (of HR/U), HREP, BG, BR, PS, DS, Y (of X/Y). VILR maximm = 0.5 V, VIL, maximun = 1.0 V and VILM m
40、inimm = -0.5 V, unless otherwise specified. In order to obtain these results all inputs must be terminated, i.e., not allowed to float. External clock input high and clack input Lou are measured at 50% of the input transition. T = Icyc/4 is used in the electrical characteristics. of the external clo
41、ck input. A clock stabilization delay is required uhen using the on-chip crystal oscillator after power-on reset and after recovering from STOP mode. Circuit stabilization deiay is required during reset when using an external clock after power-on reset and after recovering from STOP mode. For ac tes
42、ting, the follouing conditions apply: The exact length of each 1 is affected by the duty cycle SIZE 5962-89512 A REVISION LEVEL SHEET Parameters are guaranteed but not tested. Timing parameters 17 through 22 apply only to IRPA and IROB in level-sensitive mode using fast interrupts to prevent multipl
43、e interrupt service. To avoid these timing restrictions, the negative edge-triggered mode is recomnended uhen using fast interrupts. Host synchronization delay, asynchronous input signal, determine whether it is high or Lou, and synchronize it to the internal clock. Synchronous clock cycle, tSCC, (f
44、or internal clock) is determined by the SCI clock control register and Icyc. Asynchronous clock cycle, tACC, (for internal clock) is determined by the SCI clock control register and Icyc. For internal clock, external clock cycle is defined by Icyc and SSI control register. The timing waveforms in th
45、e ac electrical characteristics are tested with VIL maxim of 0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, KOA, and MOOB. These four pins are tested using the input Levels set forth in the dc electrical characteristics, except for VILR and i!, which are referenced to a device i
46、nput signal and are measured with respect to the 50% point of the respective input signals transition. The device O1 output levels are measured with VOL and VOH reference levels set at 1.0 V dc and 2.0 V dc,respectively. US= Umber of wait states (1 US = 1 tcyc) programed into the external bus access
47、 using BCR (WS=0-151. tHSDk = Host synchronization delay time. ST (CC2 pin) Transmit frame sync. bi = Bit length. u1 = Word length. Device external bus timing parameters are designed and tested at the maximun capacitive load of 50 pF, including stray capacitance. Uith no external access fran DSP. Lo
48、ng interrupts are recomnended hen using level sensitive mode. (tHSDL), is the time period required for the device to sample any external TXC (SCK pin) = Transmit clock. FSR (SCl or SC2 pin) = Receive frame sync. RXC (SCO and SCK pin) = Receive clock. During external read or write access. During exte
49、rnal read-urite-modify access. During STOP mode, external bus will not be released and BG uill not go low. During UAIT mode, external bus will not be released and BG will not go low. DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SND-5962-89532 REV C 9999996 O063667 24b STANDARD1 ZED
