1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated boilerplate for 5 year review lhl 11-08-15 CHARLES F. SAFFLE REV SHEET REV A SHEET 15 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James E. Jamison DLA LAND AND MARITIME
2、COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Ray Monnin APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE SYNCHRONOUS STA
3、TE MACHINE, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-04-11 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-89546 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962- E454-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING
4、SIZE A 5962-89546 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Ide
5、ntifying Number (PIN). The complete PIN is as shown in the following example: 5962-89546 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circui
6、t function Clock frequency 01 CY7C330-28 Programmable synchronous state machine 28 MHz 02 CY7C330-40 Programmable synchronous state machine 40 MHz 03 CY7C330-50 Programmable synchronous state machine 50 MHz 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
7、Outline letter Descriptive designator Terminals Package style X See figure 1 28 dual-in-line package 1/ Y GDFP2-F28 28 flat package 1/ 3 CQCC1-N28 28 square chip carrier style 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply vol
8、tage - -0.5 V dc to +7.0 V dc DC voltage applied to outputs in high Z - -0.5 V dc to +7.0 V dc DC input voltage - -3.0 V dc to +7.0 V dc Thermal resistance, junction-to-case (JC): Case outlines Y and 3 - See MIL-STD-1835 Case outline X - 26C/W 2/ Maximum power dissipation (PD) 3/ - 1.0 W Maximum jun
9、ction temperature (TJ) - +175C Lead temperature (soldering, 10 seconds) - +260C Storage temperature range - -65C to +150C Temperature under bias range - -55C to +125C 1.4 Recommended operating conditions. Supply voltage range (VCC) - 4.5 V dc to 5.5 V dc High level input voltage (VIH) - 2.2 V dc min
10、imum Low level input voltage (VIL) - 0.8 V dc maximum Case operating temperature range (TC) - -55C to +125C _ 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated her
11、ein. 3/ Must withstand the added PDdue to short-circuit test, e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89546 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FOR
12、M 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitatio
13、n or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFE
14、NSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphi
15、a, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtai
16、ned. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualifi
17、ed manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality
18、Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to ident
19、ify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 and figure 1 herein.
20、3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as speci
21、fied on figure 3. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, or C (see 4.3), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of th
22、e total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics
23、 are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for Resale
24、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89546 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part sha
25、ll be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.6 Processing EPLDs. All
26、 testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPLDs. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.6.2 Programmability of EPLDs. When specifi
27、ed, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5. 3.6.3 Verification of erasure or programmed EPLDs. When specified, devices shall be verified as either programmed (see 4.5 herein) to the specified pattern or erased (see 4.4 herein).
28、As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.7 Certification/compliance mark. A com
29、pliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compl
30、iance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the
31、 manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification o
32、f change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable
33、 required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89546 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-
34、3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Device type Limits Unit 4.5 V VCC 5.5 V unless otherwise specified Min Max Output high voltage VOHVCC= 4.5 V, IOH= -2.0 mA VIN= VIH= VIL1,2,3
35、 All 2.4 V Output low voltage VOLVCC= 4.5 V, IOL= 8.0 mA VIN = VIH = VIL1,2,3 All 0.5 V Input high voltage 2/ VIH1,2,3 All 2.2 V Input low voltage 2/ VIL1,2,3 All 0.8 V Input leakage current IIXVCC= 5.5 V to GND 1,2,3 All -10 +10 A Output leakage current IOZVCC = 5.5 V, IOUT= 0 mA VOUT= 5.5 V and GN
36、D 1,2,3 All -40 +40 A Output short circuit current 3/ 4/ IOSVCC= 5.5 V, VOUT= 5.5 V 1,2,3 All -30 -90 mA Power supply current ICCVCC= 5.5 V, IOUT= 0 mA VIN = GND 1,2,3 All 150 mA Input capacitance 4/ CINVIN= 2.0 V, VCC= 5.0 V TA= +25C, f = 1 Mhz (see 4.3.1c) 4 All 7 pF Output capacitance 4/ COUTVO=
37、2.0 V, VCC = 5.0 V TA= +25C, f = 1 Mhz (see 4.3.1c) 4 All 8 pF Input or feedback setup to input register clock tISVCC= 4.5 V See figures 4 and 5 9,10,11 01 10 ns 02,03 5 Input register clock to output register clock tOS9,10,11 01 35 ns 02 25 03 20 Output register clock to output. tCO9,10,11 01 25 ns
38、 02 20 03 15 Input register hold time tIH9,10,11 All 5 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89546 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A
39、SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Device type Limits Unit 4.5 V VCC 5.5 V unless otherwise specified Min Max Input register clock to output enable 5/ tCEAVCC = 4.5 V See figures 4 and 5
40、 9,10,11 01 35 ns 02 25 03 20 Input register clock to output disable 4/ 5/ tCER9,10,11 01 35 02 25 03 20 Pin 14 enable to output enable 5/ tPZX9,10,11 01 35 02 25 03 20 Pin 14 disable to output disable 4/ 5/ tPXZ9,10,11 01 35 02 25 03 20 Input or output clock width high 4/ tWH9,10,11 01 15 02 10 03
41、8 Input or output clock width low 5/ tWL9,10,11 01 15 02 10 03 8 External clock period (tCO+ tIS) input and output 4/ clock common tP9,10,11 01 35 02 25 03 20 Output data stable time from synchronous 4/ 6/ clock input tOH9,10,11 All 3 Output data stable time minus I/P 4/ 7/ register hold time tOH -
42、tIH9,10,11 All 0 External maximum frequency 4/ 8/ (1/(tCO+ tIS) fMAX19,10,11 01 28.5 MHz 02 40.0 03 50.0 Data path maximum frequency 4/ 9/ (1/(tWH+ tWL) fMAX29,10,11 01 33.3 02 45.0 03 57.0 Internal maximum frequency 4/ 10/ fMAX39,10,11 01 30.0 02 45.0 03 57.0 Provided by IHSNot for ResaleNo reprodu
43、ction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89546 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 1/ AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels
44、of 1.5 V, input pulse levels of 0 to 3.0 V, and the output load on figure 4, circuit A, unless otherwise specified. 2/ These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3/ For test purposes, not more than one output at a time shoul
45、d be shorted. Short circuit test duration should not exceed one second. VOUT= 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits spec
46、ified in table I. 5/ Measured as the time after output register disable input that the previous output data state remains stable on the output. This delay is measured to the point at which a previous high level has fallen to 0.5 V below VOHminimum or a previous low level has risen to 0.5 V above VOL
47、maximum with the load in figure 4, circuit B. See figure 5 for enable and disable test waveforms. 6/ Measured as the time after output register clock input that the previous output data state remains stable on the output. 7/ This difference parameter guarantees that any output feedback to its own inputs externally or internally will satisfy the input register minumum input hold time. This parameter is guaranteed for a given individual device. 8/ This parameter guarantees the maximum frequency at which a state machine configuration with external feedback can operate. 9/
