1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. jak 03-06-11 Thomas M. Hess B Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 10-02-12 Thomas M. Hess REV SHET REV SHET REV STATUS REV
2、B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Tim H. Noh DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFE
3、NSE CHECKED BY Ray Monnin APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 8-INPUT MULTIPLEXER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-04-25 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89599 SHEET 1 OF 12 DSCC FORM 2233
4、APR 97 5962-E202-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawi
5、ng describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89599 01 C A Drawing number Device type (see 1.2.1) Case out
6、line(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACT251 8-input multiplexer with three-state outputs, TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as desig
7、nated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 2 CQCC1-N20 20 Leadless-chip-carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3
8、 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +6.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current (IIK, IOK) . 20 mA DC output current (per pin) (IOUT) . 50 mA DC VCCor GND curren
9、t 100 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) . 500 mW Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 3/ 1.4 Recommended operating conditions. 2/ Supply voltage ran
10、ge (VCC) +4.5 V dc minimum to 5.5 V dc maximum Input voltage range (VIN) 0.0 V dc to VCCOutput voltage range (VOUT) . 0.0 V dc to VCCCase operating temperature range (TC) . -55C to +125C Input rise or fall times: VCC= 4.5 V 0.0 to 24 ns (10-90%, 10 ns) VCC= 5.5 V 0.0 to 20 ns (10-90%, 8 ns) 1/ Stres
11、ses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ Maximum junction temperature shall not be exceeded except
12、for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 432
13、18-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these doc
14、uments are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Co
15、mponent Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700
16、 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. ELECTRONIC INDUSTRIES A
17、LLIANCE (EIA) JEDEC Standard No. 20 - Standard for Description of 54/74ACXXXXX and 54/74ACTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). 2.3 Orde
18、r of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 It
19、em requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufa
20、cturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may ma
21、ke modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow optio
22、n is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal con
23、nections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,
24、 OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics
25、. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full (case or ambient) operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. Th
26、e electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD P
27、IN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indica
28、tor “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MI
29、L-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate
30、of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent
31、, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I
32、HS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ Symbol Test conditions -55C TC +125C 4.5 V VCC 5.5 V unl
33、ess otherwise specified Group A subgroups Limits 2/ Unit Min Max High-level output voltage 3006 VOH3/ VIN= VIH= 2.0 V min or VIL= 0.8 V max IOH= -50 A VCC= 4.5 V 1, 2, 3 4.4 V VCC= 5.5 V 5.4 VIN= VIH= 2.0 V min or VIL= 0.8 V max IOH= -24 mA VCC= 4.5 V 3.7 VCC= 5.5 V 4.7 VIN= VIH= 2.0 V min or VIL= 0
34、.8 V max IOH= -50 mA VCC= 5.5 V 3.85 Low-level output voltage 3007 VOL3/ VIN= VIH= 2.0 V min or VIL= 0.8 V max IOL= 50 A VCC= 4.5 V 1, 2, 3 0.1 V VCC= 5.5 V 0.1 VIN= VIH= 2.0 V min or VIL= 0.8 V max IOL= 24 mA VCC= 4.5 V 0.5 VCC= 5.5 V 0.5 VIN= VIH= 2.0 V min or VIL= 0.8 V max IOL= 50 mA VCC= 5.5 V
35、1.65 High-level input voltage VIHVCC= 4.5 V 1, 2, 3 2.0 V VCC= 5.5 V 2.0 Low-level input voltage VILVCC= 4.5 V 1, 2, 3 0.8 V VCC= 5.5 V 0.8 Input leakage current low 3009 IIL4/ VIN= 0.0 V VCC= 5.5 V 1, 2, 3 -1.0 A Input leakage current high 3010 IIH4/ VIN= 5.5 V VCC= 5.5 V 1, 2, 3 1.0 Quiescent supp
36、ly current 3005 ICCHVIN= VCCor GND VCC= 5.5 V 1, 2, 3 160 A ICCL160 ICCZ160 Quiescent supply current delta, TTL input levels 3005 ICC5/ VCC= 5.5 V For input under test VIN= VCC- 2.1 V For all other inputs VIN= VCCor GND 1, 2, 3 1.6 mA Three-state output leakage current high 3021 IOZH VIN= VCCor GND
37、VCC= 5.5 V VOUT= 5.5 V or 0.0 V 1, 2, 3 10.0 A Three-state output leakage current low 3020 IOZL -10.0 Input capacitance 3012 CINSee 4.3.1c 4 8.0 pF Power dissipation capacitance CPD6/ See 4.3.1c 4 110.0 pF Functional tests 3014 Tested at VCC= 4.5 V and repeated at VCC= 5.5 V, See 4.4.3d 7, 8 L H See
38、 footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical pe
39、rformance characteristics Continued. Test and MIL-STD-883 test method 1/ Symbol Test conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Limits 2/ Unit Min Max Propagation delay time, In to Z 3003 tPHL17/ VCC= 4.5 V CL= 50 pF RL= 500 See figure 4 9 1.0 11.5 ns 10, 1
40、1 1.0 13.5 tPLH17/ 9 1.0 11.5 10, 11 1.0 13.5 Propagation delay time, In to Z 3003 tPHL27/ 9 1.0 12.5 10, 11 1.0 15.0 tPLH27/ 9 1.0 12.0 10, 11 1.0 14.0 Propagation delay time, Sn to Z 3003 tPHL37/ 9 1.0 14.5 10, 11 1.0 18.0 tPLH37/ 9 1.0 14.5 10, 11 1.0 18.0 Propagation delay time, Sn to Z 3003 tPH
41、L47/ 9 1.0 15.5 10, 11 1.0 19.5 tPLH47/ 9 1.0 14.5 10, 11 1.0 18.5 Propagation delay time, output enable, OE to Z 3003 tPZH17/ 9 1.0 8.5 10, 11 1.0 10.0 tPZL17/ 9 1.0 8.0 10, 11 1.0 9.5 Propagation delay time, output disable, OE to Z 3003 tPHZ17/ 9 1.0 11.0 10, 11 1.0 12.5 tPLZ17/ 9 1.0 8.5 10, 11 1
42、.0 9.5 Propagation delay time, output enable, OE to Z 3003 tPZH27/ 9 1.0 8.5 10, 11 1.0 10.0 tPZL27/ 9 1.0 8.5 10, 11 1.0 10.0 Propagation delay time, output disable, OE to Z 3003 tPHZ27/ 9 1.0 12.0 10, 11 1.0 13.5 tPLZ27/ 9 1.0 7.5 10, 11 1.0 8.5 1/ For tests not listed in the referenced MIL-STD-88
43、3 (e.g. CPD), utilize the general test procedure under the conditions listed herein. All inputs and outputs shall be tested, as applicable, to the tests in table I herein. 2/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and th
44、e direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWI
45、NG SIZE A 5962-89599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. 3/ VOHand VOLshall be tested at VCC= 4.5 V. VOHand VOLare guaranteed, if not tested, for VCC= 5.5 V. Limits shown ap
46、ply to operation at VCC= 5.0 V 0.5 V. Transmission driving tests are performed at VCC= 5.5 V with a 2 ms duration maximum. 4/ VIHand VILtests are not required, and shall be applied as forcing functions for VOHand VOLtests. 5/ This test may be performed either one input at a time (preferred method) o
47、r with all input pins simultaneously at VIN= VCC- 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using the alternate test method, the maximum limits are equal to the number of inputs at a high TTL input level times 1.6 mA; and the preferred metho
48、d and limits are guaranteed. 6/ Power dissipation capacitance (CPD) determines the no load dynamic power consumption, PD= (CPD+ CL) (VCCx VCC)f + (ICCx VCC) + (n x d x ICCx VCC). The dynamic current consumption, IS= (CPD+ CL)VCCf + ICC+ n x d x ICC. For both PDand IS, n is the number of device inputs at TTL levels, f is the frequency of the input signal, and d is the duty cycle of the input signal. 7/ AC limits at VCC= 5.5 V are equal to limits at VCC= 4.5 V and guaranteed by testing at VCC= 4.5 V. The minimum ac limits are guaranteed for VCC= 5.5 V by guardbanding the VCC= 4.5 V
