1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. - lgt 01-07-13 Raymond Monnin B Redrawn. Drawing format and paragraphs updated to MIL-PRF-38535 requirements. - drw 12-08-17 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPL
2、ACED. REV SHEET REV B B B B B B SHEET 15 16 17 19 20 21 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kirby DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THI
3、S DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 8-BIT ANALOG I/O SYSTEM, MONOLITHIC SILICON DRAWING APPROVAL DATE 91-05-06 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-
4、89629 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E445-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89629 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. S
5、COPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89629 01 L A Drawing number Device
6、 type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function Relative Accuracy 01 AD7569S 8-bit analog I/O system 1 LSB for DAC and ADC 02 AD7569T 8-bit analog I/O system
7、1/2 LSB for DAC and ADC 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as spe
8、cified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage (VDD) to AGNDDACor AGNDADC-0.3 V dc to +7.0 V dc Supply voltage (VDD) to DGND -0.3 V dc to +7.0 V dc VDDto VSS. -0.3 V dc to +14 V dc AGNDDACor AGNDADCto DGND -0.3 V dc to VDD+0.3 V dc AGNDDACor AGNDADC5.0 V dc Logic v
9、oltage to DGND . -0.3 V dc to VDD+0.3 V dc CLK input voltage to DGND -0.3 V dc to VDD+0.3 V dc Output voltage to AGNDDAC1/ VSS-0.3 V dc to VDD+0.3 V dc Input voltage to AGNDADC. VSS-0.3 V dc to VDD+0.3 V dc Storage temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Powe
10、r dissipation (PD) 450 mW 2/ Thermal resistance, junction to case (JC). See MIL-STD-1835 Thermal resistance, junction to ambient (JA) . 120C/W Junction temperature (TJ) +150C 1.4 Recommended operating conditions. Supply voltage to ground (VSS). -4.75 V dc to 5.25 V dc Supply voltage to ground (VDD)
11、+4.75 V dc to +5.25 V dc Ambient operating temperature range (TA) . -55C to +125C _ 1/ Output may be shorted to any voltage in the range VSSto VDDprovided that the power dissipation of the package is not exceeded. 2/ Derate above TA= +75C at 6.0 mW/C. Provided by IHSNot for ResaleNo reproduction or
12、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89629 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification
13、, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specificat
14、ion for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copi
15、es of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cit
16、ed herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, append
17、ix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML pro
18、duct in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or fun
19、ction of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physica
20、l dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Pin descriptions. The pin descriptions shall be a
21、s specified on figure 2. 3.2.4 Truth table. The truth table shall be as specified on figure 3. 3.2.5 Input/output voltage ranges and unipolar/bipolar code tables. The input/output voltage ranges and unipolar/bipolar code tables shall be as specified on figure 4. 3.2.6 Logic diagram. The logic diagra
22、m shall be as specified on figure 5. 3.2.7 Load circuits. The load circuits shall be as specified on figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89629 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-
23、3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.2.8 Write cycle timing waveforms. The write cycle timing waveforms shall be as specified on figure 7. 3.2.9 ADC mode 1 interface timing waveforms. The ADC mode 1 interface timing waveforms shall be as specified on figure 8. 3.2.10 ADC mode 2 inte
24、rface timing waveforms. The ADC mode 2 interface timing waveforms shall be as specified on figure 9. 3.2.11 Equivalent input voltage circuit. The equivalent input voltage circuit shall be as specified on figure 10. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the el
25、ectrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in
26、 table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, t
27、he manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certifi
28、cation mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compl
29、iance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-P
30、RF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land an
31、d Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted witho
32、ut license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89629 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ CL= 100 pF to AGNDDACRL= 2.0 k -55C TA+125C Group A subgro
33、ups Device type Limits Unit unless otherwise specified Min Max DAC specifications Relative accuracy INL 01 1, 2, 3 1.0 LSB 02 1 1.0 2, 3, 12 1/2 Differential nonlinearity DNL Guaranteed monotonic 01 1, 2, 3 1.0 LSB 02 1 1.0 2, 3, 12 3/4 Unipolar offset error DAC data is all zeros, VSS= 0 V ALL 1 2.0
34、 LSB 01 2, 3 2.5 02 2, 3 2.0 1, 12 1.5 Bipolar zero offset error DAC data is all zeros, VSS= -5.0 V ALL 1 2.0 LSB 01 2, 3 2.5 02 2, 3 2.0 1, 12 1.5 Full-scale error VDD = 5.0 V 2/ ALL 1 2.0 LSB 01 2, 3 4.0 02 2, 3 3.0 12 1.0 DDVscale FullTA= +25C, VOUT= 2.5 V, VDD= 5% ALL 1 0.5 LSB SSVscale FullTA=
35、+25C, VOUT= -2.5 V, VSS= 5% ALL 1 0.5 LSB Digital input voltage low level VILALL 1, 2, 3 0.8 V Digital input voltage high level VIHALL 1, 2, 3 2.4 V Input leakage current IILVIN= 0 to VDDALL 1, 2, 3 10 A Positive power supply current IDDVOUT= VIN= 2.5 V, Logic units = 2.4 V, CLK = 0.8 V, output unlo
36、aded ALL 1, 2, 3 13 mA Negative power supply current (dual supply) ISSVOUT= VIN= -2.5 V, Logic units = 2.4 V, CLK = 0.8 V, output unloaded ALL 1, 2, 3 4.0 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR
37、OCIRCUIT DRAWING SIZE A 5962-89629 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ CL= 100 pF to AGNDDACRL= 2.0 k -55C TA+125C Group A subgroups Device type Limits Un
38、it unless otherwise specified Min Max DAC specifications - continued Input capacitance CINSee 4.3.1d ALL 4 10 pF Signal-to-noise ratio SNR VOUT= 20 kHz full scale sine wave with fSAMPLING= 400 kHz 01 4, 5, 6 44 dB 02 46 Total harmonic distortion THD VOUT= 20 kHz full scale sine wave with fSAMPLING=
39、400 kHz ALL 4, 5, 6 48 dB Functional test See 4.3.1b ALL 7, 8 WR pulse width t1See figure 7 3/ ALL 9 80 ns 10, 11 90 CS , BA to WR setup time t2ALL 9, 10, 11 0 CS , BA to WR hold time t3ALL 9, 10, 11 0 Data valid to WR setup time t4ALL 9 60 10, 11 80 Data valid to WR hold time t5ALL 9, 10, 11 10 ADC
40、 specifications Relative accuracy INL 01 1, 2, 3 1 LSB 02 2, 3, 12 1/2 1 1 Differential nonlinearity DNL No missing codes 01 1, 2, 3 1 LSB 02 2, 3, 12 3/4 1 1 Unipolar offset error VSS = 0 V ALL 1 2.0 LSB 01 2, 3 3.0 02 2, 3 2.5 1, 12 1.5 Bipolar zero offset error VSS= -5.0 V, 1.25 V range ALL 1 3.0
41、 LSB 01 2, 3 4.0 02 2, 3 3.5 12 2.5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89629 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234
42、 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ fCLK= 5.0 MHz -55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max ADC specifications - continued Full scale error VDD = 5.0 V 2/ ALL 1 -4.0 0 LSB 2, 3 -7.5 2.0 DDVscal
43、e FullVIN = 2.5 V, VDD = 5% ALL 1 0.5 LSB SSVscale FullVIN = -2.5 V, VSS = 5% ALL 1 0.5 LSB Input voltage low level VILALL 1, 2, 3 0.8 V Input voltage high level VIHALL 1, 2, 3 2.4 V Analog input current IINSee figure 10 ALL 1, 2, 3 300 A Input leakage current IILCS , RD , ST , Range, RESET ALL 1, 2
44、, 3 10 A CLK input current low level IINLVIN= 0 V ALL 1, 2, 3 -1.6 mA CLK input current high level IINHVIN= VDDALL 1, 2, 3 40 A Output voltage low level VOLISINK= 1.6 mA ALL 1, 2, 3 0.4 V Output voltage high level VOHISOURCE= 200 A ALL 1, 2, 3 4.0 V Floating state leakage current IOUTALL 1, 2, 3 10
45、A Positive power supply current IDDVOUT= VIN= 2.5 V, Logic units = 2.4 V, CLK = 0.8 V, output unloaded ALL 1, 2, 3 13 mA Negative power supply current (dual supplies) ISSVOUT= VIN= -2.5 V, Logic units = 2.4 V, CLK = 0.8 V, output unloaded ALL 1, 2, 3 4.0 mA Input capacitance CINSee 4.3.1d ALL 4 10 p
46、F Floating state output capacitance COUTSee 4.3.1d ALL 4 10 pF Signal-to-noise ratio SNR VIN= 100 kHz full scale sine wave with fSAMPLING= 400 kHz 4/ 01 4, 5, 6 44 dB 02 45 Total harmonic distortion THD VIN= 100 kHz full scale sine wave with fSAMPLING= 400 kHz 4/ ALL 4, 5, 6 48 dB Conversion time wi
47、th external clock fCLK = 5.0 MHz ALL 9, 10, 11 2.0 s Conversion time with internal clock ALL 9, 10, 11 1.6 2.6 s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89629 DLA LAND A
48、ND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ fCLK= 5.0 MHz -55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max ADC specifications - continued Functional test See 4.3.1b ALL 7, 8 ST pulse width t6See figure 8 3/ ALL 9, 10,
