1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R078-94. 94-03-24 Michael Frye B Drawing updated to reflect current requirements. - lgt 01-08-13 Raymond Monnin C Redrawn. Drawing format and paragraphs updated to MIL-PRF-38535 requirements. - drw 12-11-27 Cha
2、rles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Rick C. Officer DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil
3、 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, CMOS, 12-BIT ANALOG-TO-DIGITAL CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-08-04 AMS
4、C N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-89679 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E096-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89679 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990
5、REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the followi
6、ng example: 5962-89679 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 CS5012 12-bit CMOS analog-to-digital converter, 12.25 s
7、1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 Dual-in-line X CQCC1-N44 44 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535,
8、 appendix A. 1.3 Absolute maximum ratings. 1/ Positive digital supply (+VD) voltage range -0.3 V dc to +6.0 V dc 2/ Negative digital supply (-VD) voltage range . +0.3 V dc to -6.0 V dc Positive analog supply (+VA) voltage range -0.3 V dc to +6.0 V dc Negative analog supply (-VA) voltage range +0.3 V
9、 dc to -6.0 V dc Analog ground (AGND) to digital ground (DGND) . 0.5 dc Input current, any pin except supplies . 10 mA 3/ Analog input voltage (AIN and VREFpins) -VA0.3 V dc to +VA+0.3 V dc Digital input voltage . -0.3 V dc to +VD+0.3 V dc Storage temperature range . -65C to +150C Lead temperature (
10、soldering, 10 seconds) +260C Junction temperature (TJ) +195C Power dissipation Case Q . 1500 mW Case X . 1100 mW Thermal resistance, junction to case (JC). See MIL-STD-1835 Thermal resistance, junction to ambient (JA) Case Q . 45C/W Case X . 60C/W _ 1/ All voltages referenced to AGND and DGND tied t
11、ogether. 2/ In addition +VDmust not be greater than +VA+ 0.3 V dc. 3/ Transient currents of up to 100 mA will not cause latch-up. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89679 DLA LAND AND MARITIME CO
12、LUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 1/ Ambient operating temperature range (TA) . -55C to +125C Positive digital supply voltage (+VD) +4.5 V dc to +VA2/ Negative digital supply voltage (-VD) . -4.5 V dc to -5.5 V dc Positive an
13、alog supply voltage (+VA) +4.5 V dc to +5.5 V dc Negative analog supply voltage (-VA) -4.5 V dc to -5.5 V dc Digital ground (DGND) 0 V dc Analog ground (AGND) . 0 V dc Digital input low voltage (VIL) . -0.3 V dc to +0.8 V dc Digital input high voltage (VIH) . +2.0 V dc to +VDAnalog reference input v
14、oltage (VREF) range . +2.5 V dc to +4.5 V dc Analog input voltage range: Unipolar mode . AGND to +VREFBipolar mode . -VREFto +VREF2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the e
15、xtent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Met
16、hod Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla
17、.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing i
18、n this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89679 DLA LAND AND MARITIME COLUMBUS, OHIO 4
19、3218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualif
20、ied Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PR
21、F-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark i
22、n accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall b
23、e in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Block diagram. The block diagram shall be as specified on figure 3. 3.3 Electrical performance charac
24、teristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The
25、 electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PI
26、N number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicat
27、or “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL
28、-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformanc
29、e. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verific
30、ation and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for
31、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89679 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TA +
32、125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Resolution for which no missing codes is guaranteed RES 1/ 1, 2, 3 01 12 Bits Integral linearity error INL 1/, 2/ 1, 2, 3 01 0.5 LSB Differential linearity error DNL 1/, 2/ 1, 2, 3 01 0.5 LSB Full-scale error FSE 1/, 2
33、/ 1, 2, 3 01 0.5 LSB Full-scale error drift dFSE/dt1/, 2/, 3/, 4/ 2, 3 01 0.25 LSB Unipolar offset error VOFF 1/, 2/ 1, 2, 3 01 0.5 LSB Unipolar offset error drift dVOFF/dt1/, 2/, 3/, 4/ 2, 3 01 0.25 LSB Bipolar offset error BOFF 1/, 2/ 1, 2, 3 01 0.5 LSB Bipolar offset error drift dBOFF/dt1/, 2/, 3
34、/, 4/ 2, 3 01 0.25 LSB Bipolar negative full-scale error BNFSE 1/, 2/ 1, 2, 3 01 0.5 LSB Bipolar negative full-scale error drift dBNFSE/dt1/, 2/, 3/, 4/ 2, 3 01 0.25 LSB Peak harmonic or spurious noise S/PN 1 kHz input, full scale amplitude, bipolar mode 1/, 2/ 4, 5, 6 01 84 dB 12 kHz input, full sc
35、ale amplitude, bipolar mode 1/, 2/ 80 Signal to noise ratio S/(N+D) 1 kHz input, full scale amplitude, bipolar mode 1/, 2/ 4, 5, 6 01 72 dB Analog input capacitance in fine charge mode CINUnipolar mode, TA= +25C 1/, 3/ 4 01 375 pF Bipolar mode, TA= +25C 1/, 3/ 220 Digital input voltage (HOLD , CLKIN
36、, CAL, INTRLV , BW, RST, UPBP , AO, RD , CS ) VIH5/, 6/ 1, 2, 3 01 2.0 V VIL0.8 Digital input current IIN5/, 6/ 1, 2, 3 01 10 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-8
37、9679 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TA +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Digital output voltage (D
38、0 D15, SDATA, SCLK, EDC , EOT ) VOLLogic “0”, ISINK= -1.6 mA 5/, 6/ 1, 2, 3 01 0.4 V VOHLogic “1”, ISOURCE= 100 A 5/, 6/ +VD-1.0 High impedance state output current IOZPins D0to D15only 5/, 6/ 1, 2, 3 01 10 A Conversion time tC1/, 6/, 7/ 9, 10, 11 01 12.25 s Acquisition time tACQTA= +25C 1/, 2/, 3/,
39、 8/ 9 01 3.75 s Throughput tPUT1/, 2/, 6/ 9, 10, 11 01 62.5 kHz Positive analog supply current IA+VA, +VD= 5.5 V, -VA, -VD= -5.5 V 6/, 9/ 1, 2, 3 01 19.0 mA Negative analog supply current IA-+VA, +VD= 5.5 V, -VA, -VD= -5.5 V 6/,9/ 1, 2, 3 01 19.0 mA Positive digital supply current ID+VA, +VD= 5.5 V,
40、 -VA, -VD= -5.5 V 6/, 9/ 1, 2, 3 01 6.0 mA Negative digital supply current ID-+VA, +VD= 5.5 V, -VA, -VD= -5.5 V 6/, 9/ 1, 2, 3 01 6.0 mA Master clock frequency 10/ fCLKInternally generated, CLKIN = 0 V dc, +VD, +VA= 4.5 V, -VD-VA= -4.5 V, TA= -55C 11 01 1.75 MHz HOLD pulse width tHPW(see figure 4) 5
41、/, 6/, 11/ 9, 10, 11 01 1/fCLK +50 tCns Data delay time tDD(see figure 4) 5/, 6/, 11/ 9, 10, 11 01 100 ns EOC pulse width tEPW(see figure 4) 5/, 6/, 11/ 9, 10, 11 01 4/fCLK -20 ns CAL, INTRLV to CS low setup time tCS(see figure 5) 5/, 6/, 11/ 9, 10, 11 01 20 ns A0 to CS and RD low setup time tAS(see
42、 figure 5) 5/, 6/, 11/ 9, 10, 11 01 20 ns CS or RD High to A0 invalid hold time tAH(see figure 5) 5/, 6/, 11/ 9, 10, 11 01 50 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-
43、89679 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TA +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max CS High to CAL, INTRLV i
44、nvalid hold time tCH(see figure 5) 5/, 6/, 11/ 9, 10, 11 01 50 ns CS low to data valid access time tCARD = logic “0”, (see figure 5) 5/, 6/, 11/ 9, 10, 11 01 250 ns RD low to data valid access time tRACS = logic “0”, (see figure 5) 5/, 6/, 11/ 9, 10, 11 01 250 ns Output float delay tFD(see figure 5)
45、 5/, 6/, 11/ 9, 10, 11 01 250 ns SDATA to SCLK rising setup time tSS(see figure 6) 5/, 6/, 11/ 9, 10, 11 01 2/fCLK -50 ns SCLK rising to SDATA hold time tSH(see figure 6) 5/, 6/, 11/ 9, 10, 11 01 2/fCLK -100 ns 1/ +VA, +VD= +5.0 V; -VA, -VD= - 5.0 V; VREF= +2.5 V dc or +4.5 V dc; fCLK= 4 MHz; Analog
46、 source impedance = 200 ; Error tests are done after calibration at the temperature of interest. 2/ Synchronous sampling mode (EOT connected to HOLD ), interleave disabled. 3/ This parameter shall be measured only for initial characterization and after process or design changes which may affect this
47、 parameter. 4/ Total drift over -55C to +125C since calibration at power-up at +25C. 5/ +VA, +VD= +5.0 V dc 10%; -VA, -VD= -5.0 V dc 10%. 6/ This parameter is guaranteed, if not tested, at TA= +25C. This parameter is tested at TA= -55C and +125C. 7/ Measured from falling transition on HOLD to fallin
48、g transition on EOC . 8/ Acquisition time is the time allowed by the converter for acquisition of the input voltage prior to conversion. 9/ All outputs unloaded; All inputs swinging between +VDand 0 V dc. 10/ Externally supplied maximum clock frequency is 4 MHz. Analog parametric measurements are done with the maximum external clock (see footnote 1/). 11/ Inputs: logic “0” = 0 V, logic “1” = +VD; CL= 50 pF. Provided by IHSNot for R
