1、Y 4 I LTR i SMD-5962-89758 59 W 999999b OOLL569 9 i DATE (YR-MO-DA) APPROVED DESCRIPTION REVISIONS I I REV SHEET REV SHEET 15 REV STATUS REV OF SHEETS 12 3 4 5 6 7 8 9 1011 121314 SHEET PREPARED BY DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 PMIC N/A STANDARDIZED MILITARY DRAWING MICROCIRCU
2、ITS, DIGITAL, FAST, 9-BIT BUFFERED NON-INVERTING LATCH, THREE- STATE OUTPUT, MONOLITHIC SILICON THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE 5962-89758 ANSC N/A ISION LEVEL 1 OF 15 I SHEET I I )ESC FORW 193 JUL 91 5962-ES1 7-92 DISTRIBUTION STATEMENT
3、 A. Approved for public release; distribution is unlimited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-89758 59 9999996 0011570 5 I I. i i Device type (1.2.4. :I .1 byawjng number 12.1 DevTce type(?.). The device TypeTS) shall identlyy
4、. 2 circuit Tunction as POih3ws: Device type Generic number .cmgj3 f.WC%$?G O1 02 o3 54F CT45A 9-bit buffered nnn-%we with three-state output 9-b?t buffered hOrkhVt2 three-state output, TTL compaaibie Pb4t bufTered Bon-lmerting iatch, rri th three-state output, T74 cmpat“ite 5 4F T843C Supply voitag
5、e range- - - = - - - - - - - - - - - Input voitsage range- - - - - - - = - - - - - - - - - Output voltage range - - - - - - - a - - - - - - - - bC input ,diade curmnt O - - - - - - - - - - - - bt output rdlade current (io e.g., los. STANDAWEZED DES% P-liM P93A JUL 91 Provided by IHSNot for ResaleNo
6、reproduction or networking permitted without license from IHS-,-,-2. APPLICABLE DOCUMENTS SMD-5962-87758 59 W 9999996 0011571 7 I 2.1 Government specification, standard, and bulletin. Unless otherwise specified, the following specification, standard, and bulletin of the issue listed in that issue of
7、 the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent Specified herein. SPECIFICATION MILITARY MIL-M-38510 - Microcircuits, General Specification for. STANDARD MILITARY MIL-STD-883 - Test Methods and Procedures for M
8、icroelectronics. BULLETIN MILITARY MIL-BUL-103 - List of Standardized Military Drawings (SMDs) (Copies of the specification, standard, and bulletin required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contr
9、acting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with 1.2.1 of NIL-STD
10、-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“ and as specified herein. 3.2 Desiqn, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-M-38510 and herein. 3.2.1 Terminal connections. 3.2.2
11、 Truth table. The terminal connections shall be as specified on figure 1. The truth table shall be as specified on figure 2. 3.2.3 Loqic diagram. 3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. The logic diagram shall be as
12、 specified on figure 3. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II.
13、 The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shall be marked with the PIN listed in 1.2 herein. herein). In addition, the manufacturers PIN may also be marked as listed in MIL-BUL-103 (see 6.
14、6 STANDARDIZED 5962-89758 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-8975B 59 I 9999996 0011572 9 T TABLE I. Electrical perf ormance characteri
15、st ics. I I I I Test I Symbol High level output i VOH vo 1 tage I I I I I I Low level output IVOL vo 1 tage l Input clamp voltage IvIK I High level input I IIH current I Low level input IIIL cur rent I High irnpedence output current 1 IOZH I- Short circuit Qutput current Quiescent power supply i ICC
16、Q current (CMOS I I inputs) Quiescent power supply I delta current (TTL inputs) 1 Icc See footnotes at end of table. I J Limits 1 Unit l I I Conditions IDevice IGroup A -55OC 5 TC 5 +125OC I type Isubgroups I I I Vcc = 5.0 V dc *IO% I I I Min I Max I unless otherw LIcc f 4.5 v, VIH - 2.0 v LIIL I 0.
17、8 V, vcc = 4.5 v, VIH - 2.0 v VIL f 0.8 V, ,e specified I I I I I I I I I I 1 I I I I I I I 1 I I I I III I I III IOH -300pA I All I I, 2, 3 I 4.3 I I V IOH = -15 mA I ALL I 1, 2, 3 I 2.4 I I IoL = 300 pA I ALL I 1, 2, 3 I I 0.21 V III I ,I I I l I I I II I I III I I III IoL = 32 mA I All I 1, 2, 3
18、I 1 .5; LIcc = 4.5 V, IIN = -18 mA i All 1 1, 2, 3 i i -1.21 V I l I I I I I I I I I I I III I I I I I I I III I I I I I I I I I I I III vcc = 5.5 v, VIN = 5.5 v I All I 1, 2, 3 I I 5.01 pA Jcc = 5.5 V, VIN = GND I All I 1, 2, 3 1 I -5.01 pA dcc = 5.5 v, VIN = 5.5 v I All I 1, 2, 3 I I 10 I /JA iCc
19、= 5.5 V, VIN = GND I ALL I I, 2, 3 I (-ia I PA iOUT - GND I I I ALL I 1, 2, 3 1 -75 I I mA =-5.5 I/ I I III III IIN f 0.2 V or VIN 2 5.3 V, I All I 1, 2, 3 I I 1.51 mA I I Icc - 5.5 V, fI = O MHz I I I I III I I III Icc = 5.5 v, VIN = 3.4 v 2/ I ALL I 1, 2, 3 I I 2-01 mA DEFENSE ELECTRONICS SUPPLY C
20、ENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-9758 59 E 9979996 0011573 O I TABLE I. E lectri ca 1 performance characteri st i cs - continued. I I evice IGroup A type I subgroups Test ymbol Li
21、mits L Unit II - II II II L II Min I Max I I 0.251 mA/ I IHHz I 4.0 I Conditions Vcc = 5.0 V dc *IO% -55OC 5 TC 5 +125“C unless otherwise specified - Vcc =.5.5 V, OE = GND, One bit toggling 50% duty cycle, VIN 2 5.3 V or VIN 5 0.2 V, Outputs open, LE = Vcc 3/ I AL1 I 1, 2, 3 I l Iynamic power supply
22、 current CCD cc I I I I All I 1, 2, 3 Total power supply current vcc = 5.5 v, outputs open, f = 10 MHz, 56% duty cycle, se bit toggling, OE = GND, LE = Vcc 4/ V 5.3 v IN or VIN 5 0.2 v I I ALL I I 2i VIN 2 3.4 v or VIN = GND I I I 1 I I U I I I U I I I U I I All I 4 All I 4 All 7, 8 O1 I 9,10,11 03
23、01. I 9,10,11 03 O1 L9,10,11 03 O1 L 9,10,11 02 03 I See 4.3.1 Input capacitance IN OUT PLHI .PHLI Output capacitance See 4.3.1 Functional tests See 4.3.ld L II CL = 50 pF minimum RL = 50Q 5/ See figure 4 1.5 I lO.O ns 1.5 I 7.51 II Propagation delay time Dn to Yn, LE = High II 1.5 I 6.31 II 1.5 I 1
24、3.01 ns II Propagation delay time LE to Yn PLH2 tPHL2 1.5 i l0.5L 1.5 I 6.81 1.5 1 14.01 ns 1.5 I lO.OL 1.5 I 9.01 II II II II 1.5 II I 14.01 ns II II 1.5 1 11.01 1.5 I 10.01 Propagation delay time PRE to Yn tPLH3/ Propagation delay time CLR to Yn tPHL3 See footnotes at end of tab SIZE 5962-89758 ST
25、ANDARDIZED DEFENSE ELECTRONICS SUPPLY CENTER MILITARY DRAWING A DAYTON, OHIO 45444 REVISION LEVEL SHEET 5 I I I DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5b2-89758 59 W 7979b OOLL574 2 TABLE 1. Test hQut enable time, O
26、E to Yn 5/ 3uQut disable time, OE to Yn 5/ Setup time, Dn to LE Hold time, Dn to LE Recovery time, PRE tO Yh ReEery t.ime, CLR to Yn See footnotes at end of tab1 jymbol tPZH/ t PZL tPHZ tPLZ t S th t tREC2 Electrical performance characteristics - Continued. Conditions -55C 5 TC 5 t125“C vcc = 5.0 V
27、dc *IO% unleCs otherwise specified RL = Som, cL = 50 pF minimum, see figure 4 I I I I U I I I I I o1 I 9,10,11 I I 02 I I I o3 I I I I 02 I I I o3 I I I I 02 I I I o3 I levice !Group A type I subgroups O1 L9,10,11 03 O1 L9,10,11 03 O1 I 9,10,11 O1 I 9,10,11 I I I 02 I I I o3 I O1 I 9,10,11 I II all
28、other inputs at Vcc or GND. 3/ This parameter is not directly testable, but is derived for use in total power supply calculations. Icc = ICCQ t (delta Icc x DH x NT) + (ICCD x fI x NI) where: 41 D, = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH fI = Input frequency in MHZ NI = Numb
29、er of inputs at fI - 5/ The minimum limits are guaranteed, if not tested, to the limits specified in table I. I STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 t- DESC FORM 193A JUL 91 5962-89758 REVISION LEVEL. SHEET Provided by IHSNot for ResaleNo reproduction or
30、 networking permitted without license from IHS-,-,-SMD-5962-87758 59 I 9999996 0011576 b I 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-BUL-103 (see 6.6 herein). DESC-ECS prior to listing
31、 as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-STD-883 (see 3.1 herein) and the requirements herein. The certificate of compliance submitted to 3.7 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (see 3.1
32、 herein) shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DESC-ECS shall be required in accordance with MIL-STD-883 (see 3.1 herein). 3.9 Verification and review. DESC, DESCs agent, and the acquiring activity retain the
33、 option to review the manufacturers facility and applicable required documentation. at the option of the reviewer. Offshore documentation shall be made available onshore 4, QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with sectio
34、n 4 of MIL-M-38510 to the extent specified in MIL-STD-883 (see 3.1 herein). 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test,
35、method 1015 of MIL-STD-883. (1) Test condition A, 8, C, or D using the circuit subm herein). tted with the certificate of compliance (see 3.6 (2) TA = +125OC, minimum. Interim and final electrical test parameters shall be as Specified in table II herein, except interim electrical parameter tests pri
36、or to burn-in are optional at the discretion of the manufacturer. b. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of YIL-STD-883 includ4ng groups.A, 8, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A ins
37、pection. a. b. c. Tests shall be as specified in table II herein. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. subgroup 4 (CI, and COUT measurements) shall be measured only for the initial test and after process or design changes which may affect capacitance. at a frequ
38、ency of 1 MHz. Test all applicable pins on five devices with zero failures. Subgroups 7 and 8 tests shall verify the truth table as specified on figure 2. Capacitance shall be measured between the designated terminal and GND d. STANDARDIZED SIZE 5962-89758 MILITARY DRAWING A DEFENSE ELECTRONICS SUPP
39、LY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 8- . DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-89758 59 I 999999b 0033577 8 SIZE STANDARDIZED DEFENSE ELECTRONICS SUPPLY CENTER MILITARY DRAWING A DAYTON, OHIO 454
40、44 REVISION LEVEL Device types 5962-89758 SHEET 9 ace outlines Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 01, 02 and 03 I L and K I 3 Ter mi na 1 symbol - OE DO DI D2 D3 D4 D5 D6 D7 D8 CLR GND LE PRE Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO - - vcc - - - - - NC OE D
41、O DI D2 D3 D4 NC D5 D6 D7 D8 CLR GND NC LE PRE Y7 Y6 Y5 NC Y4 Y3 Y2 Y1 YO - - - ya vcc PIN DESCRIPTION - CLR - When E is low, the outputs are low if is low. - When CLR is high, data can be entered into the latch. Dn - The latch data inputs. LE - The latch enable input. - Yn - The three-state latch o
42、utputs. OE - The ogput enable control. The latches are transparent when LE is high. When is low, the outputs ar enabled. Input data is latched on the high-to-low transition. - PRE - Preset line. When OE is high, thgutputs (Yn) are in the high impedance (off) state. Preset overrides CLR. WhenRE is lo
43、w, the outputs are high if OE is Low. FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-87758 59 9999996 0033578 T I I I I-I-I-I I I I I I CLR I PRE I OE I LE 1 Dn 1 Yn I I J I I IlII I I I H I H I HI XI XI 2 I
44、HighZ I I I IlII I I I H I H I HI HI LI 2 I HighZ I I IlII I I I H I H I HI HI HI 2 I HighZ I I I IlII I I I I IlIl I I I I IlII I I I I IlII I I I I IlII I I I I I IlII I ILIHILIXIXI L I I I IlII I I FUNCTION 1 I I OUTPUTSI INPUTS I H I H 1 H 1 L I X I 2 ILatched (High 2)I I H I H I L 1 H 1 L I L 1
45、 Transparent 1 I H I H I L I H I H I H I Transparent I I H I H I L I L I X I NC I Latched I IH(L(LX(X( H 1 Preset 1 Clear I ILILILIXIXI H I Preset I I I IlII I I I L I H I H I L I X I Z (Latched (High Z)( 2 Latched (High Z)l I H I L I HI LI XI I I I I IlII H 5 High voltage level L = Low voltage leve
46、l X = Irrelevant Z = High impedence NC = No Change FIGURE 2. Truth table. STANDARDIZED SIZE 5962-89758 ,. -. ., MILITARY DRAWING a DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET o DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted wi
47、thout license from IHS-,-,-SMD-59b2-89758 59 9999996 0011579 1 ! j YO Yi Y2 Y3 Y4 Y5 YN-i YN FIGURE 3. Logic diagram. DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NOIES: I. 2, 3, RL = Lqad pesic_top, 5aM4 or equivalent. CL =
48、Load qqxzeitanva, 5Q pF mipimum, ipcludes prob R = Termkmtion registance; sho.uid be equal tct ZouT f and jig. capacitance. pulse generatw. I SUITCH POSITION 1 - -I Swttch I I - 1- -1 _ Test I I Open drain _ I Clowd- I - “. - - i I Closed - _ 1 111. dher outputs I _ Open- .- FJGURE, 4, Test circuit- and syitchinp_aueftms. e Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-, SMD-5762-89758 59 I 9999996 OOL15L T I i 3.0 V 1.5 v 0.0 v INPUT TIMING 1.5 v 0.0 v INPUT ASYNCHRONOUS CONTROL 3.0 V 1.5 V 0.0 v PRESET CLEAR ETC SYN
