1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout jak. 05-10-03 Thomas M. Hess B Add footnote 5/ for test condition of total power supply current (ICC) to table I. - LTG 10-02-12 Thomas M.
2、Hess REV SHET REV SHET REV STATUS REV B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Marcia B. Kelleher DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AN
3、D AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Monica L. Poelking APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, FAST CMOS, INVERTING OCTAL BUFFER/LINE DRIVER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-09-12 AMSC N/A REVISION LEVEL B SIZE A C
4、AGE CODE 67268 5962-89767 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E138-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89767 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET
5、 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89767
6、 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54FCT540 Inverting octal buffer/line driver with three-state outputs, TTL com
7、patible inputs 02 54FCT540A Inverting octal buffer/line driver with three-state outputs, TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-i
8、n-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC +
9、 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc DC input diode current (IIK) -20 mA DC output diode current (IOK) . -50 mA DC output current (IOUT) . 100 mA Maximum power dissipation (PD) 2/ . 500 mW Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Storage temperatu
10、re range (TSTG) . -65C to +150C Junction temperature (TJ) +175C Lead temperature (soldering, 10 seconds) +300C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Maximum low level input voltage (VIL) 0.8 V dc Minimum high level input voltage (VIH) . 2.0 V dc Case
11、 operating temperature range (TC) . -55C to +125C 1/ Unless other wise specified, all voltages are referenced to ground. 2/ Must withstand the added power dissipation due to short circuit test, e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
12、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89767 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
13、 of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDAR
14、DS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available on
15、line at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawi
16、ng takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B de
17、vices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manuf
18、acturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifi
19、cations shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specifie
20、d in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagra
21、m. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW
22、ING SIZE A 5962-89767 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the
23、 full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The pa
24、rt shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification
25、/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3
26、.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm tha
27、t the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notificat
28、ion of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation
29、 shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89767 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FOR
30、M 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC+125C unless otherwise specified VCCDevice type Group A subgroups Limits Unit Min Max High level output voltage VOHVIH= 2.0 V VIL= 0.8 V IOH= -300 A 4.5 V All 1, 2, 3 4.3 V IOH= -12 mA 2.4 Low level
31、output voltage VOLVIH= 2.0 V VIL= 0.8 V IOL= +300 A 4.5 V All 1, 2, 3 0.2 V IOL= +48 mA 0.55 Input clamp voltage VIKIIN= -18 mA 4.5 V All 1, 2, 3 -1.2 V High level input current IIHVIN= 5.5 V 5.5 V All 1, 2, 3 5.0 A Low level input current IILVIN= GND 5.5 V All 1, 2, 3 -5.0 A High impedance output c
32、urrent IOZHVIN= 5.5 V 5.5 V All 1, 2, 3 10.0 A IOZLVIN= GND 5.5 V All 1, 2, 3 -10.0 A Short circuit output current IOS1/ VOUT= GND 5.5 V All 1, 2, 3 -60.0 mA Quiescent power supply current (CMOS inputs) ICCQVIN 0.2 V or VIN 5.3 V fi= 0.0 MHz 5.5 V All 1, 2, 3 1.5 mA Quiescent power supply current (T
33、TL inputs) ICC2/ VIN= 3.4 V 5.5 V All 1, 2, 3 2.0 mA Dynamic power supply current ICCDOEx = GND One bit toggling, 50% duty cycle VIN 5.3 V or VIN 0.2 V Outputs open 5.5 V All 3/ 0.4 mA/ MHz Total power supply current ICC4/ 5/ OEx = GND Outputs open fi= 10 MHz One bit toggling 50% duty cycle VIN 5.3
34、V or VIN 0.2 V 5.5 V All 1, 2, 3 5.5 mA VIN= 3.4 V or VIN GND 5.5 V All 1, 2, 3 6.0 mA Input capacitance CINSee 4.3.1c All 4 10 pF Output capacitance COUTSee 4.3.1c All 4 12 pF Functional tests See 4.3.1d 4.5 V All 7, 8 Propagation delay time, Dn to On tPHL, tPLHCL= 50 pF RL= 500 See figure 4 6/ 4.5
35、 V 01 9, 10, 11 2.0 9.5 ns 02 2.0 5.1 Propagation delay time, output enable, OEx to On tPZH, tPZL4.5 V 01 9, 10, 11 2.0 12.5 ns 02 2.0 6.5 Propagation delay time, output disable, OEx to On tPHZ, tPLZ4.5 V 01 9, 10, 11 2.0 12.5 ns 02 2.0 5.9 See footnotes on next sheet. Provided by IHSNot for ResaleN
36、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89767 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. 1/ Not more than one
37、output should be shorted at one time and the duration of the short circuit condition should not exceed 1 second. 2/ TTL driven input (VIN= 3.4 V); all other inputs at VCCor GND. 3/ This parameter is not directly testable but is derived for use in total power supply calculations. 4/ ICC= ICCQ+(ICCDHN
38、T)+(ICCDfiNI) where: DH= Duty cycle for TTL inputs high NT= number of TTL inputs at DH fi= input frequency, in megahertz; NI= number of inputs at fi. 5/ For ICCtest in an ATE environment, the effect of parasitic output capacitive loading from the test environment must be taken into account, as its e
39、ffect is not intended to be included in the test results. The impact must be characterized and appropriate offset factors must be applied to the test result. 6/ The minimum limits are guaranteed, if not tested, to the limits specified in table I. Device types 01 and 02 Case outlines R, S, and 2 Term
40、inal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OEA D0 D1 D2 D3 D4 D5 D6 D7 GND O7 O6 O5 O4 O3 O2 O1 O0 OEB VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWIN
41、G SIZE A 5962-89767 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Inputs Output OEA OEB Dn On L L L H L L H L H H X Z L = Low voltage level H = High voltage level X = Irrelevant Z = High impedance FIGURE 2. Truth table. FIGURE 3. Logic diagra
42、m. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89767 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. When measuring tPLH, tPHL, tPZH, and
43、tPHZ: S1 = Open. When measuring tPZLand tPLZ: S1 = Closed. 2. RL= 500, load resistor. 3. CL= 50 pF or equivalent (includes test jig and probe capacitance). 4. RT= Terminal resistance, should be equal to ZOUTof the pulse generator. 5. Diagram shown for input control enable-low and input control disab
44、le-high. 6. Pulse generator for all pulses: tr 2.5 ns; tf 2.5 ns. FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89767 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,
45、 OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conduct
46、ed on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made av
47、ailable to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameter
48、s shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) - Final electrical test parameters (method 5004) 1*, 2, 3, 7, 8, 9, 10, 11 Group A test requirements (method 5005) 1, 2, 3, 4, 7, 8, 9, 10, 11 Groups C and D end-point electrical parameters (metho
