DLA SMD-5962-91521 REV C-2005 MICROCIRCUIT LINEAR 12-BIT DATA ACQUISITION SYSTEM 4-CHANNEL SIMULTANEOUS SAMPLING MONOLITHIC SILICON《硅单块 4沟道同步装置 12比特数据获取系统 直线式微型电路》.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R230-94. 94-08-12 M. A. Frye B Changes in accordance with NOR 5962-R148-97. 96-12-20 Raymond Monnin C Incorporate revision A and B N.O.Rs. Update drawing to current requirements. Editorial changes throughout. -

2、 drw 05-01-06 Raymond Monnin REV SHET REV C SHET 15 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra Rooney DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles E. Besore COLUMBUS, OHIO 43218-3990 http:

3、/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY M. A. Frye MICROCIRCUIT, LINEAR, 12-BIT DATA ACQUISITION SYSTEM, 4-CHANNEL AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-11-30 SIMULTANEOUS SAMPLING, MONOLITHIC SILICON AMSC N/A REVISION LEVEL C S

4、IZE A CAGE CODE 67268 5962-91521 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E064-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91521 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL

5、C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Ide

6、ntifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 91521 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designator

7、Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, ap

8、pendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 AD7874 12-bit data acquisition system, 4-channel simu

9、ltaneous sampling 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcir

10、cuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 3

11、 CQCC1-N28 28 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC

12、IRCUIT DRAWING SIZE A 5962-91521 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Positive supply voltage range (VDD) to AGND -0.3 V dc to +7.0 V dc Positive supply voltage range (VDD) to DGND -0.3 V dc to +7.0 V

13、 dc Negative supply voltage range (VSS) to AGND. +0.3 V dc to -7.0 V dc AGND to DGND. -0.3 V dc to VDD+ 0.3 V dc Analog input voltage range (VIN) -15.0 V dc to +15.0 V dc Voltage reference output (REF OUT) to analog ground range (AGND). 0 V dc to VDDLogic input voltage range . -0.3 V dc to VDD+ 0.3

14、V dc Logic output voltage range. -0.3 V dc to VDD+ 0.3 V dc Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Maximum power dissipation (PD) 2/ . 1,000 mW Lead temperature (soldering, 10 seconds). +300C Storage temperature range -65C to +150C 1.4 Recommended operating conditions. Positive

15、 supply voltage range (VDD) . +4.75 V dc to +5.25 V dc Negative supply voltage range (VSS) -4.75 V dc to -5.25 V dc Analog input voltage range (VIN) -10.0 V dc to +10.0 V dc Reference input voltage range . +2.85 V dc to +3.15 V dc Ambient operating temperature range (TA) -55C to +125C 2. APPLICABLE

16、DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF

17、 DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 -

18、 List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphi

19、a, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtai

20、ned. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Above TA= +75C, derate 10 mW/C for case outline X. Above TA= +66C, derate 10 mW/C for case outline 3. Provided by

21、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91521 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item re

22、quirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requir

23、ements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device

24、 classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as spe

25、cified on figure 2. 3.2.4 Timing diagram. The timing diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as s

26、pecified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked

27、 with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, th

28、e RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “Q

29、ML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to

30、 the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as

31、 an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of

32、 conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of

33、product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and appli

34、cable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 93 (see MIL-PRF-38535, appendix A). Provided

35、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91521 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symb

36、ol Conditions 1/ -55C TA +125C +4.75 V VDD +5.25 V -5.25 V VSS -4.75 V Group A subgroups Device type Limits 2/ Unit unless otherwise specified Min Max SAMPLE AND HOLD Acquisition time to 0.01 pct tACQ3/, 4/, See figure 3 9, 10, 11 All 2.0 s Aperture delay tAU9, 10, 11 -10 40 ns Aperture delay matchi

37、ng ADM 4.0 SAMPLE AND HOLD AND ADC DYNAMIC PERFORMANCE Signal-to-noise ratio SNR fIN= 10 kHz sine wave, fSAMPLE= 29 kHz 1, 2, 3 All 70 dB Total harmonic distortion THD -78 Peak harmonic PH Intermodulation distortion 2ndorder terms IMD2 fA= 9 kHz, fB= 9.5 kHz, fSAMPLE= 29 kHz 3rdorder terms IMD3 Chan

38、nel-to-channel isolation ISO DC ACCURACY Relative accuracy INL 4/ 1, 2, 3 All 1 LSB Differential nonlinearity DNL 4/ No missing codes guaranteed Positive full-scale error 5/ PFSE Any channel 5 Negative full-scale error 5/ NFSE Full-scale error match FSEM Between channels 5 Bipolar zero error BZE Any

39、 channel 5 Bipolar zero error match BZEM Between channels 4 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91521 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISI

40、ON LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C +4.75 V VDD +5.25 V -5.25 V VSS -4.75 V Group A subgroups Device type Limits 2/ Unit unless otherwise specified Min Max ANALOG INPUTS 6/ Analog input current

41、AIN 1, 2, 3 All 600 A REFERENCE OUTPUT VDD= +5 V, VSS= -5 V Reference output voltage error ROVE 1 All 0.33 % 2, 3 1.0 Reference output load change ROLC Reference load current change (0-500 microamps) 1, 2, 3 2.0 mV REFERENCE INPUT Reference input current RIC VREF= +3 V 1, 2, 3 All 1.0 A Reference in

42、put capacitance CREFTA= +25C 4 10 pF LOGIC INPUTS High level logic input voltage VINH7/ 7, 8 All 2.4 V Low level logic input voltage VINL0.8 Logic input current IINVIN= 0 V to VDD, VDD= +5.25 V, VSS= -5.25 V 1, 2, 3 10 A Logic input capacitance CINTA= +25C 4 10 pF LOGIC OUTPUTS High level logic outp

43、ut voltage VOH1, 2, 3 All 4.0 V Low level logic output voltage VOL0.4 Logic output floating-state leakage current LOFSLC VIN= 0 V to VDD, VDD= +5.25 V, VSS= -5.25 V DB0 DB11 10 A Logic output floating-state output capacitance COUTTA= +25C 4 10 pF See footnotes at end of table. Provided by IHSNot for

44、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91521 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol

45、 Conditions 1/ -55C TA +125C +4.75 V VDD +5.25 V -5.25 V VSS -4.75 V Group A subgroups Device type Limits 2/ Unit unless otherwise specified Min Max POWER REQUIREMENTS VDD= +5.25 V, VSS= -5.25 V Positive supply current IDDCS = RD = CONVST = +5.0 V 1, 2, 3 All 18 mA Negative supply current ISS12 Powe

46、r dissipation PDVDD= +5 V, VSS= -5 V 150 mW AC CHARACTERISTICS 8/ CONVST pulse width t1TA= +25C, See figure 3 9/ 9 All 50 ns CS to RD setup t20 RD pulse width t3See figure 3 9, 10, 11 70 CS to RD hold t4TA= +25C, See figure 3 9/ 9 0 RD to INT delay t560 Data access time after RD t6See figure 3 10/ 9

47、, 10, 11 70 Bus relinquish time after RD t7See figure 3 11/ 5 50 Delay times between reads t8TA= +25C, See figure 3 9/ 9 150 CONVST to INT , external clock = 2.5 MHz tCONVTA= +25C, See figure 3 9/ 9 All 31.0 32.5 s CONVST to INT , internal clock tCONV31.0 35.0 Minimum input clock period tCLK TA= +25

48、C 9/ 10 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91521 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. 1/ VREF= +3 V, AGND = DGND = 0 V. All tests are guaranteed over a supply voltage range of VDD= +5 V 5%, VSS= -5 V 5%, ho

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