1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated to current boilerplate for 5 year review. lhl 12-07-27 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A A A A SHEET 15 16 17 18 19 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1
2、 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles Reusing
3、APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS EE PROGRAMMABLE READ ONLY MEMORY 256 X 16, MONOLITHIC SILICON DRAWING APPROVAL DATE 91-08-16 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91549 SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E401-12 Provided by IHSNot for ResaleNo re
4、production or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of hig
5、h reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. Th
6、e PIN is as shown in the following example: 5962 - 91549 01 M P A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA
7、 marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 D
8、evice type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 93CS66 4096-Bit serial electrically erasable programmable memory 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance
9、level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s).
10、The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style P GDIP1-T8 or CDIP2-T8 8 Dual-in-line package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix
11、A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ All in
12、put or output voltages with respect to GND . -0.3 V dc to +6.5 V Storage temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Junction temperature (TJ) 2/ . +150C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA) . +
13、200C/W Power dissipation (PD) . 80 mW Endurance . 10,000 program/erase cycles (minimum) Data retention 10 years (minimum) 1.4 Recommended operating conditions. Positive power supply +4.5 V to +5.5 V Ambient operating temperature range (TA) -55C to +125C Supply voltage (VSS) 0.0 V dc High level input
14、 voltage range (VIH) . 2.0 V dc to VCC +1.0 V dc Low level input voltage range (VIL) . -0.1 V dc to 0.8 V dc Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks for
15、m a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE
16、 STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are avai
17、lable online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this dr
18、awing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performa
19、nce and affect reliability. 2/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD
20、 MICROCIRCUIT DRAWING SIZE A 5962-91549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as
21、 modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B dev
22、ices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case out
23、line shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Instruction set. The instruction set shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless
24、 otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified
25、 in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitatio
26、ns, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-3853
27、5, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classe
28、s Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source o
29、f supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and here
30、in or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits
31、 delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review f
32、or device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3
33、.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number xxx (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW
34、ING SIZE A 5962-91549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 5 DSCC FORM 2234 APR 97 3.11 Processing of EEPROMs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.11.1 Conditions of the supplied
35、devices. Devices will be supplied in cleared state (Logic “0s”). No provision will be made for supplying written devices. 3.11.2 Read-write procedures. Correct red-write procedures shall be as specified 4.6.3. 3.11.3 Verification of state of EEPROMs. When specified, devices shall be verified as eith
36、er written to the specified pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be removed
37、from the lot or sample. 3.11.4 Power supply sequence of EEPROMs. In order to reduce the probability of inadvertent writes, the following power supply sequences shall be observed: a. A logic low state shall be applied to CS at the same time or before the application of VCC. b. A logic low state shall
38、 be applied to CS at the same time or before the removal of VCC. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 6 DSCC FORM 2234 APR
39、 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C Vss = 0 V; 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Supply current active CMOS level ICC1 VCC = 5.5 V, VSK = 0, fSK = .5 MHz, VCS = 5 V, VI = 0 or 5 V 1, 2, 3
40、 01 2 mA Supply current active TTL level ICC2 VCC = 5.5 V, VSK = .8 to 2 V fSK = .5 MHz, VCS = VIH VI = VIH/L 1, 2, 3 01 4 Supply current CMOS standby ICC3 VCC = 5.5 V, VSK = 0 to 5 V fSK = 0 MHz, VCS = 0 V, other VI = VIH/L 1, 2, 3 01 100 A Logical “0” input leakage current IIL VCC = 5.5 V, VI = 0
41、V 1, 2, 3 01 -10 Logical “1” input leakage current IIH VCC = 5.5 V, VI = 5.5 V 1, 2, 3 01 10 Logical “0” input leakage current IOLZ VCC = 5.5 V, DO TRI-STATE, VDO = 0 V 1, 2 , 3 01 -10 Logical “1” output leakage current IOHZ VCC = 5.5 V, DO TRI-STATE, VDO = 5.3 V 1, 2, 3 01 10 Logical “0” input volt
42、age VIL VCC = 4.5 V 1, 2, 3 01 -.1 .8 V Logical “1” input voltage VIH VCC = 5.5 V 1, 2, 3 01 2 VCC +1 Logical “0” output voltage VOL1 VCC = 4.5 V, IOL = 1.8 mA 1, 2, 3 01 .4 VOL2 VCC = 4.5 V, IOL = 10 A .2 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking perm
43、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C Vss = 0 V; 4.5 V VCC 5.5 V
44、 unless otherwise specified Group A subgroups Device type Limits Unit Min Max Logical “1” output voltage VOH1 VCC = 4.5 V, IOH = -400 A 1, 2, 3 01 2.4 V VCC = 4.5 V, IOH = -10 A VCC -0.2 Input capacitance CI VCC = 5.5 V, VIN = 2 V, f = 1 MHz 1/ 4 01 8 pF Output capacitance CO VCC = 5.5 V, VO = 2 V,
45、f = 1 MHz 1/ 4 01 10 AC Testing 2/ SK clock frequency fSK VCC = 4.5 V 3/ 9, 10, 11 01 0 0.5 MHz SK high time tSKH VCC = 4.5 V 3/ 9, 10, 11 01 500 ns SK low time tSKL VCC = 4.5 V 3/ 9, 10, 11 01 500 CS low time tCS VCC = 4.5 V 4/ 9, 10, 11 01 500 CS setup time tCSS VCC = 4.5 V, Relative to SK rising
46、See figure 3 9, 10, 11 01 100 DI setup time tDIS 9, 10, 11 01 200 PRE setup time tPRES 9, 10, 11 01 100 PE setup time tPES 9, 10, 11 01 100 CS hold time tCSH VCC = 4.5 V Relative to SK falling 9, 10, 11 01 0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking pe
47、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91549 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C Vss = 0 V; 4.5 V VCC 5.5
48、 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max DI hold time tDIH VCC = 4.5 V, Relative to SK rising See figure 3 9, 10, 11 01 200 ns PE hold time tPEH VCC = 4.5 V, Relative to CS falling See figure 3 9, 10, 11 01 500 PRE hold time tPREH 9, 10, 11 01 0 Output delay to “1” tPD1 VCC = 4.5 V, Relative to SK rising See figure 3 9, 10, 11 01 1000 Output delay to “0” tPDO 9, 10, 11 01 1000 CS to status valid tSV 9, 10, 11 01 1000 CS to DO in tri-state tDF VCC = 5.5
