1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R171-95 95-08-02 Michael A. Frye B Changes in accordance with NOR 5962-R025-96 95-12-22 Michael A. Frye C Update drawing to current requirements. Editorial changes throughout. - gap 01-05-14 Raymond Monnin D Up
2、date drawing to current requirements. Editorial changes throughout. tcr 09-05-29 Joseph Rodenbeck REV SHET REV D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Tuan Nguyen DEFENSE
3、SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218 - 3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, CMOS, 1K X 8 PARALLEL SYNCHRONOUS FIFO, MONOLITHIC SILICON AND AGENCI
4、ES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-08-31 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-93138 SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E321-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING
5、SIZE A 5962-93138 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A ch
6、oice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 93138 01 M X A Federal stock
7、class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with th
8、e appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device
9、 type Generic number Circuit function Access time 01 72220L50 1K X 8 CMOS Parallel Synchronous FIFO 50 ns 02 72220L35 1K X 8 CMOS Parallel Synchronous FIFO 35 ns 03 72220L25 1K X 8 CMOS Parallel Synchronous FIFO 25 ns 1.2.3 Device class designator. The device class designator is a single letter iden
10、tifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF
11、-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CDIP3-T28 or GDIP4-T28 28 Dual-in-line Y GDFP2-F28 28 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for
12、device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93138 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3
13、DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Terminal voltage with respect to ground . -0.5 V dc to +7.0 V dc DC output current 50 mA Storage temperature range . -65C to +135C Maximum power dissipation (PD) 1.25 W Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-
14、to-case (JC): See MIL-STD-1835 Junction temperature (TJ). +175C 1.4 Recommended operating conditions. Supply voltage (VCC) . 4.5 V dc to 5.5 V dc Supply voltage (GND) . 0 V Input high voltage (VIH) 2.2 V dc minimum Input low voltage (VIL) . 0.8 V dc maximum Case operating temperature range (TC) -55C
15、 to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or
16、 contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE
17、HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA
18、 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD
19、MICROCIRCUIT DRAWING SIZE A 5962-93138 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues
20、of the documents are the issues of the documents cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http
21、:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a confli
22、ct between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requ
23、irements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirem
24、ents for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device c
25、lasses Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified
26、 on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range
27、. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be m
28、arked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be
29、in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shal
30、l be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certific
31、ate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers p
32、roduct meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device c
33、lass M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93138 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, O
34、HIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limit Unit unless otherwise specified Min Max Input leakage current ILI0.4 V VIN VCC1, 2, 3 All -10 +10 A
35、Output leakage current ILOOE VIH, 0.4 VOUT VCC1, 2, 3 All -10 +10 A Output high voltage VOHIOH= -2 mA 1, 2, 3 All 2.4 V Output low voltage VOLIOL= 8 mA 1, 2, 3 All 0.4 V Active power supply ICCf = 20 MHz, outputs open 1, 2, 3 All 180 mA current Input capacitance CINVIN= 0 V, f = 1.0 MHz, TA= +25C, s
36、ee 4.4.1e 4 All 10 pF Output capacitance COUTVOUT= 0 V, f = 1.0 MHz, with output deselected ( OE = high), TA= +25C, see 4.4.1e 4 All 10 pF Functional tests See 4.4.1c 7, 8A, 8B All Clock cycle frequency fs 9, 10, 11 01 20 MHz 02 28.6 03 40 Data access time tA9, 10, 11 01 3 25 ns 02 3 20 03 3 15 Cloc
37、k cycle time tCLK9, 10, 11 01 50 ns 02 35 03 25 Clock high time tCLKH9, 10, 11 01 20 ns 02 14 03 10 Clock low time tCLKL9, 10, 11 01 20 ns 02 14 03 10 Data setup time tDS9, 10, 11 01 10 ns 02 8 03 6 First read latency time tFRLCL= 30 pF, input pulse levels = GND to 3.0 V; input rise/fall times = 3 n
38、s; input timing reference levels = 1.5 V; output timing reference levels =1.5 V; see figure 3 and 4 9, 10, 11 All 1/ ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93138 DEF
39、ENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limit Unit unless otherwise specified Min Max Data hold t
40、ime tDH9, 10, 11 01, 02 2 ns 03 1 Enable setup time tENS9, 10, 11 01 10 ns 02 8 03 6 Enable hold time tENH9, 10, 11 01, 02 2 ns CL= 30 pF, input pulse levels = GND to 3.0 V; input rise/fall times = 3 ns; input timing reference levels = 1.5 V; output timing reference levels = 1.5 V; see figure 3 and
41、4 03 1 Reset pulse width 2/ tRS9, 10, 11 01 50 ns 02 35 03 25 Reset setup time tRSS9, 10, 11 01 50 ns 02 35 03 25 Reset recovery time tRSR9, 10, 11 01 50 ns 02 35 03 25 Reset to flag and output tRSF9, 10, 11 01 50 ns time 02 35 03 25 Output enable to output in low Z 3/tOLZ9, 10, 11 All 0 ns Output e
42、nable to output tOE9, 10, 11 01 3 23 ns valid 02 3 15 03 3 13 Output enable to output tOHZ9, 10, 11 01 3 23 ns in high Z 3/ 02 3 15 03 3 13 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING S
43、IZE A 5962-93138 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limit Unit unless otherwise specified
44、 Min Max Write clock to full flag tWFFCL= 30 pF, input pulse levels 9, 10, 11 01 30 ns = GND to 3.0 V; input rise/fall 02 20 times = 3 ns; input timing 03 15 Read clock to empty flag tREFreference levels = 1.5 V; 9, 10, 11 01 30 ns output timing reference levels 02 20 = 1.5 V; see figure 3 and 4 03
45、15 Read clock to almost- tAE9, 10, 11 01 30 ns empty flag 02 20 03 15 Write clock to almost-full tAF9, 10, 11 01 30 ns flag 02 20 03 15 Skew time between read tSKEW19, 10, 11 01 15 ns clock and write clock 02 12 for empty flag & full flag 03 10 Skew time between read tSKEW29, 10, 11 01 45 ns clock a
46、nd write clock for 02 42 almost-empty flag & 03 40 almost-full flag 1/ When tSKEW2 the minimum limit, tFRL(maximum) = tCLK+ tSKEW2. When tSKEW2 the minimum limit, tFRL(maximum) = either 2tCLK+ tSKEW2or tCLK+ tSKEW2. The latency timing applies only at the empty boundary ( EF = LOW). 2/ Pulse widths l
47、ess than the minimum values specified are not allowed. 3/ If not tested, shall be guaranteed to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93138 DEFENSE SUPPLY CENTER COL
48、UMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device type All Case outline X, Y Terminal number Terminal symbol 1 D4 2 D3 3 D2 4 D1 5 D0 6 AF 7 AE 8 GND 9 RCLK 10 REN 11 OE 12 EF 13 FF 14 Q0 15 Q1 16 Q217 Q3 18 Q4 19 Q5 20 Q6 21 Q7 22 VCC23 WCLK 24 WEN 25 RS 26 D7 27 D6 28 D5 FIGURE 1. Terminal connections. Provided by IHSNot for Resal
