1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to meet current MIL-PRF-38535 requirements. - glg 13-09-06 Charles Saffle REV SHEET REV A SHEET 15 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LA
2、ND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Raj Pithadia COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUITS, DIGITAL, MEMORY, CMOS, EXTENDED VOLTAGE, UV ERASABLE, PROGRAMMABLE LOGIC A
3、RRAY, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-10-08 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-93245 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E558-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS
4、-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93245 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space applicat
5、ion (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 932
6、45 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic
7、 number Circuit function tPD01 22V10 22-input 10-output AND-OR-logic array 25 ns 02 22V10 22-input 10-output AND-OR-logic array 30 ns 03 22V10L 22-input 10-output AND-OR-logic array 30 ns 04 22V10L 22-input 10-output AND-OR-logic array 35 ns 1.2.3 Device class designator. The device class designator
8、 is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and
9、qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat package 1/ L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1/ 3 CQCC1-N28 28 Leadless ch
10、ip carrier 1/ 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 2/ Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range . -2.0 V dc to +7.0 V dc 3/ Output voltage applied -0.5 V dc to +7.0 V dc 3/ Output sink current 16 mA Therm
11、al resistance, junction-to-case (JC) See MIL-STD-1835 Maximum power dissipation (PD) 4/ 1.2 W Maximum junction temperature . +175C Lead temperature (soldering, 10 seconds maximum) . +300C Data retention. 10 years (minimum) Endurance 50 cycles (minimum) Provided by IHSNot for ResaleNo reproduction or
12、 networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93245 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) . 3.0 V dc to 5.5 V dc High level input v
13、oltage (VIH) . 2.0 V dc minimum Low level input voltage (VIL) 0.8 V dc maximum Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the
14、extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Me
15、thod Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearc
16、h.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are
17、the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publication
18、s should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Bouleva
19、rd, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precede
20、nce. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Lid shall be transparent to p
21、ermit ultraviolet light erasure. 2/ All voltages referenced to VSS. 3/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 4/ Must withstand the added
22、 PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93245 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.
23、1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as d
24、escribed herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as speci
25、fied in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Unprogram
26、med devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in group A, B, or C inspections (see 4.3), the devices shall be programmed by the manufacturer prior to test with a minimum of 50 percent of the tota
27、l number of gates programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.5 Programmed devices. The requirements for supplying programmed devices are not part of this drawing. 3.3 Electrical performance characteristics. Unless
28、 otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests fo
29、r each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feas
30、ible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be repl
31、aced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 h
32、erein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of c
33、onformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA
34、Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EPLDS. All testing requireme
35、nts and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EPLDS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.10.2 Programmability of EPLDS. When specified, devices shal
36、l be programmed to the specified pattern using the procedures and characteristics specified in 4.5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93245 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISI
37、ON LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.10.3 Verification of erasure of programmability of EPLDS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that
38、 all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.11 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitors. This reprogrammability test shall b
39、e done for initial characterization and after any design or process changes which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed in section 1.3 herein over the full military te
40、mperature range. The vendors procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data. 3.12 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This te
41、st shall be done for initial characterization and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendors procedur
42、e shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93245 DLA LAND AND
43、 MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ VSS= 0 V, 4.5 V VCC 5.5 V -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max High level output VOHIO=
44、-0.4 mA 1, 2, 3 All 2.4 V voltage Low level output VOLIO= 6.0 mA 1, 2, 3 All 0.5 V voltage High impedance output IOZVCC= 5.5 V and 1, 2, 3 All -10 10 A leakage current 2/ VO= 5.5 V, VO= GND High level input IIHVIH= 5.5 V 1, 2, 3 All 10 A current VIH= 2.4 V 1, 2, 3 All 10 A Low level input current II
45、LVIL= 0.4 V 1, 2, 3 All -10 A VIL= GND 1, 2, 3 All -10 A Supply current ICCVCC= 5.5 V 1, 2, 3 01, 02 100 mA 03, 04 15 Output short circuit IOSVCC= 5.5 V 1, 2, 3 All -30 -90 mA current 3/ Input capacitance CIVI= 0 V, VCC= 5.0 V 4 All 6 pF 4/ 5/ TA= +25C, f = 1 MHz (see 4.4.1e) Output capacitance COVI
46、= 0 V, VCC= 5.0 V 4 All 12 pF 4/ 5/ TA= +25C, f = 1 MHz (see 4.4.1e) Functional testing See 4.4.1c 7, 8A, 8B All Input or feedback to tPDVCC= 4.5 V, CL= 50 pF 9, 10, 11 01 25 ns nonregistered output See figure 4, circuit B and 02, 03 30 figure 5 04 35 Clock to output tCO9, 10, 11 01 14 ns 02, 03 17
47、04 20 Input to output enable tEAVCC= 4.5 V, CL= 5 pF 9, 10, 11 01 25 ns See figure 4, circuit A and 02, 03 30 04 35 Input to output disable tER9, 10, 11 01 25 ns 02, 03 30 04 35 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I
48、HS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93245 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ VSS= 0 V, 4.5 V VCC 5.5 V -55C TC +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Clock pulse width tWVCC= 4.5 V, CL= 50 pF 9, 10, 11 01 6 ns 4/ 6/ See figure 4, circuit B and 02, 03 7 figure 5 0
