1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. - rrp 02-01-11 R. Monnin B Redrawn. Paragraphs updated to MIL-PRF-38535 requirements. - drw 13-11-14 Charles F. Saffle REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B B OF SHEETS SHEET 1
2、 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Sandra Rooney DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Sandra Rooney APPR
3、OVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 16-BIT SERIAL/BYTE D/A CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 94-06-22 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-94633 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E045-14 Provided by IHSNot for ResaleNo reproduction or networking pe
4、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94633 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device cla
5、sses Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in th
6、e following example: 5962 - 94633 01 M L A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet th
7、e MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device
8、type identifies the circuit function as follows: Device type Generic number Circuit function 01 AD660S 16-bit serial/byte DACPORT 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documen
9、tation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 as follows:
10、 Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or netw
11、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94633 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ VLLto DGND -0.3 V to +7 V dc VCCto AGND . -0.3 V to +17.0 V dc VEEto AGND +0.3
12、 V to -17.0 V dc AGND to DGND . 1 V Digital inputs (Pins 5-12 and 14-19) to DGND . -1.0 V to +7.0 V dc REF IN to AGND . 10.5 V Span/Bipolar Offset to AGND 10.5 V REF OUT, VOUT. Indefinite short to AGND, DGND, VCC, VEE, and VLLPower dissipation (PD) at TA= 60C 2/ 1000 mW Storage temperature -65C to +
13、150C Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA) 80C/W 1.4 Recommended operating conditions. VLLmax +5 V dc VCC/VEE15 V dc Ambient operating temperature range (TA) -55C to +125C 2. APPLICABLE
14、 DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT O
15、F DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103
16、- List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedenc
17、e. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute max
18、imum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Derate linearly above TA= +60C at 8.7 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC
19、ROCIRCUIT DRAWING SIZE A 5962-94633 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as m
20、odified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devic
21、es and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outli
22、ne shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post
23、irradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I.
24、3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device.
25、For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for
26、 device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 list
27、ed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance sub
28、mitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and he
29、rein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For
30、 device class M, notification to DLA Land and Maritime -VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Ma
31、ritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices
32、covered by this drawing shall be in microcircuit group number 56 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94633 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION
33、 LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VEE= -15 V VLL= +5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Resolution RES 2/ 1 01 16 Bits Relative accuracy RA 1 01 2 LSB
34、 2, 3 4 Differential nonlinearity DNL Major carry errors 1 01 2 LSB 2, 3 4 Gain error AEAll bits on 3/, 4/ 1 01 0.1 % of FSR Gain drift TCAEAll bits on 3/ 2, 3 01 25 ppm/C Unipolar offset error VOSAll bits off 1 01 2.5 mV Unipolar offset tempco TCVOSAll bits off 2, 3 01 3 ppm/C Bipolar zero error BP
35、ZEMSB on, all others off 1 01 7.5 mV Bipolar zero tempco TCBPZEMSB on, all others off 2, 3 01 5 ppm/C Reference output voltage VREF1 01 9.99 10.01 V Reference output drift TCVREF2, 3 01 25 ppm/C Reference output external current IVREF2/, 5/ 1 01 2 mA Reference output capacitive load CLVREF2/ 1 01 10
36、00 pF Reference input resistance RIN2/ 1 01 7 13 k Bipolar offset input resistance RINBPO 2/ 1 01 7 13 k Output voltage range VOUTUnipolar range 2/ 1 01 +10 V Bipolar range 2/ 10 Output current IOUT2/ 1 01 5 mA Capacitive load CL2/ 1 01 1000 pF Output voltage settling time tSL20 V step, TA= +25C 2/
37、9 01 13 s Digital input high voltage VIH1, 2, 3 01 2 V Digital input low voltage VIL1, 2, 3 01 0.8 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94633 DLA LAND AND MARITIME
38、COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VEE= -15 V VLL= +5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Digital input high
39、 current IIHVIH= +5.5 V 1, 2, 3 01 10 A Digital input low current IILVIL= 0 V 1, 2, 3 01 10 A Power supply current ILLVIH= +5.5 V, VIL= 0 V 1 01 2 mA VIH= +2.4 V, VIL= 0.4 V 7.5 ICC18 IEE-18 Power supply rejection ratio PSRR +14.25 V VCC +15.75 V 1 01 2 ppm/% -14.25 V VEE -15.75 V 2 +4.5 V VLL +5.5
40、V 2 Total harmonic distortion Sample rate = 96 kHz 1 01 0.009 % -20 dB, 990.5 Hz; Sample rate = 96 kHz 0.056 -60 dB, 990.5 Hz; Sample rate = 96 kHz 5.6 Signal-to-noise ratio SNR 1 01 83 dB Chip select t CSSee figure 2A, 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 40 ns 10, 11 50 Data set-up tDSSee figure 2A, 2/
41、VIH= 2.4 V, VIL= 0.4 V 9 01 40 ns 10, 11 50 Data hold tDHSee figure 2A, 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 0 ns 10, 11 10 Byte enable set-up tBESSee figure 2A, 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 40 ns 10, 11 50 Byte enable hold tBEHSee figure 2A, 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 0 ns 10, 11 10 LDAC hold tLHSe
42、e figure 2A, 2B 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 80 ns 10, 11 100 LDAC width tLWSee figure 2A, 2B 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 40 ns 10, 11 50 Serial clock tCLKSee figure 2B, 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 80 ns 10, 11 100 Serial clock low tLOSee figure 2B, 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 30 ns 10, 1
43、1 50 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94633 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical per
44、formance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VEE= -15 V VLL= +5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Serial clock high tHISee figure 2B 2/, VIH= 2.4 V, VIL= 0.4 V 9 01 30 ns 10, 11 50 Serial set-up tSSSee figure 2B
45、2/ VIH= 2.4 V, VIL= 0.4 V 9 01 0 ns 10, 11 10 Serial hold tSHSee figure 2B 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 0 ns 10, 11 10 Data set-up tDSSee figure 2B 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 40 ns 10, 11 50 Data hold tDHSee figure 2B 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 0 ns 10, 11 10 Clear width t CLRSee figure 2C
46、 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 80 ns 10, 11 110 Clear set-up time tSETSee figure 2C 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 80 ns 10, 11 110 Clear hold time tHOLDSee figure 2C 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 0 ns 10, 11 10 Serial out propagation delay time tPROPSee figure 2D 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 50
47、 ns 10, 11 100 Data set-up tDSSee figure 2D 2/ VIH= 2.4 V, VIL= 0.4 V 9 01 50 ns 1/ For 16-bit resolution, 1 LSB = 0.0015% or FSR = 15 ppm of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR = 30 ppm of RSR. For 14-bit resolution, 1 LSB = 0.006% of FSR = 60 ppm of FSR. FSR stands for Full-Scale Ran
48、ge and is 10 V in unipolar mode and 20 V in bipolar mode. 2/ Guaranteed if not tested. 3/ Gain error and gain drift are measured using the internal reference. 4/ Measured with fixed 50 resistors. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar mode) or 0.50% of FSR (Bipolar mode). 5/ External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET. Provided by IHSNot for ResaleNo reproductio
