1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redraw. Update drawing to current requirements. drw 10-01-20 Charles F. Saffle REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Marcia Kelleher DEFENSE SUPPLY CENTE
2、R COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Rajesh Pithadia APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL-LINEAR, QUAD, 8-BIT VOLTAGE OUTPUT SER
3、IAL D/A CONVERTER WITH FEEDBACK, MONOLITHIC SILICON DRAWING APPROVAL DATE 95-12-05 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-95512 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E145-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M
4、ICROCIRCUIT DRAWING SIZE A 5962-95512 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (d
5、evice class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 95512 01 Q
6、 R A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
7、 are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as
8、follows: Device type Generic number Circuit function 01 DAC0854 Quad, 8-bit voltage output serial D/A converter with feedback 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentati
9、on M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 and as follows:
10、 Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or netw
11、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95512 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage (AVCC, DVCC) 7 V Supply voltage difference (AVCC- DVCC
12、) 5.5 V Voltage at any pin 2/ GND 0.3 V to AVCC/DVCC+ 0.3 V Input current at any pin 2/ 5 mA Package input current 3/ 20 mA Storage temperature range -65C to +150C Junction temperature (TJ) . +150C Lead temperature (soldering, 10 seconds) . 260C Power dissipation (PD) . 105 mW Thermal resistance, ju
13、nction-to-case (JC) . See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA) 86C/W 1.4 Recommended operating conditions. Supply voltage range (V+) 3.0 V V+ 15.5 V Ambient operating temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbo
14、oks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, M
15、anufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Stand
16、ard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text o
17、f this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the de
18、vice. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ When the input voltage (VIN) at any pin exceeds the power supply rails (VINV+) the absolute value of the current at that pin should be limited to 5 mA or less. 3/ The sum of the currents at all pins tha
19、t are driven beyond the power supply voltages should not exceed 20 mA. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95512 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 D
20、SCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not
21、 affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, an
22、d physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be
23、as specified on figure 1. 3.2.3 Mode selection tables. The truth table(s) shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter li
24、mits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part sh
25、all be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using th
26、is option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V
27、shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order
28、 to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior
29、to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A c
30、ertificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA
31、of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facil
32、ity and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 80 (see MIL-PRF-38535, appendix
33、 A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95512 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristic
34、s. Test Symbol Conditions 1/ -55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Resolution RES fCLK= 10 MHz 1, 2, 3 01 8 Bits Monotonicity MON 1, 2, 3 01 8 Bits Integral linearity error ILERR1, 2, 3 01 -1.0 1.0 LSB Differential linearity error DLERR1, 2, 3 01 -
35、1.0 1.0 LSB Fullscale error FSERR1, 2, 3 01 -35 +35 mV Zero error ZERR1, 2, 3 01 -35 +35 mV Power supply sensitivity VSEN1, 2, 3 01 -34 dB Logical “1” input voltage VINHAVCC= DVCC= 5.5 V 1, 2, 3 01 2.0 V Logical “0” input voltage VINLAVCC= DVCC= 4.5 V 1, 2, 3 01 0.8 V Digital input leakage current I
36、IL1, 2, 3 01 5.0 A Logical “1” output voltage VOUTHISOURCE= 0.8 mA 1, 2, 3 01 2.4 V Logical “0” output voltage VOUTLISINK= 3.2 mA 1, 2, 3 01 0.4 V Interrupt pin output voltage VINT10 k pullup 1, 2, 3 01 0.4 V Supply current ISOutputs unloaded 1, 2, 3 01 19 mA Input resistance RIN1, 2, 3 01 4 10 k Ou
37、tput reference voltage VOREFCL= 220 F 2/ 1, 2, 3 01 2.597 2.703 V Line regulation VRLINE4.5 V VCC 5.5 V, IL= 4 mA, CL= 220 F 1, 2, 3 01 5 mV Load regulation VREF/ IL0 mA IL 4 mA, CL= 220 F 1, 2, 3 01 15 mV Positive voltage output settling time tS+CL= 220 F, See figure 3 4, 5, 6 01 2.1 s See footnote
38、s at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95512 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance
39、 characteristics - continued. Test Symbol Conditions 1/ -55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Negative voltage output settling time tS-CL= 200 F 4, 5, 6 01 2.7 s Data setup time tDSSee figure 3 9, 10, 11 01 10 ns Data hold time tDHSee figure 3 9, 1
40、0, 11 01 0 ns Control setup time tCSSee figure 3 9, 10, 11 01 15 ns Control hold time tCHSee figure 3 9, 10, 11 01 0 ns Clock frequency fCLK9, 10, 11 01 10 MHz Minimum clock high time tH9, 10, 11 01 20 ns Minimum clock low time tL9, 10, 11 01 40 ns Output Hi-Z to valid 1 tCZ1See figure 3 9, 10, 11 0
41、1 37 ns Output Hi-Z to valid 0 tCZ0See figure 3 9, 10, 11 01 42 ns CS to output Hi-Z “1” t1H10 k with 60 pF 9, 10, 11 01 130 ns CS to output Hi-Z “0” t0H10 k with 60 pF 9, 10, 11 01 117 ns 1/ AVCC= DVCC= 5 V, VREF= 2.65 V, VBIAS= 1.4 V, fCLK= 10 MHz, RL= 2 k. RLis load resistors on the analog output
42、s: VOUT1, VOUT2, VOUT3, VOUT4. 2/ Output voltage limit is VOREFnominal 2%. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95512 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET
43、 7 DSCC FORM 2234 APR 97 Device type 01 Case outline R Terminal number Terminal symbol 1 VOUT22 VBIAS13 CS 4 AU 5 CLK 6 DO 7 GND 8 INT 9 DI10 DVCC11 VOUT412 VREF413 VBIAS214 VOUT315 VREF316 VOREF17 AVCC18 VREF119 VOUT120 VREF2FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproducti
44、on or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95512 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 SB RD/ WR G U A1 A0 Description Bit # 1 Bit # 2 Bit # 3 Bit # 4 Bit # 5 Bit # 6 1 0 0 0 0 0
45、Write DAC 1, no update of DAC outputs 1 0 0 0 0 1 Write DAC 2, no update of DAC outputs 1 0 0 0 1 0 Write DAC 3, no update of DAC outputs 1 0 0 0 1 1 Write DAC 4, no update of DAC outputs 1 0 0 1 0 0 Write DAC 1, update DAC 1 on CS rising edge 1 0 0 1 0 1 Write DAC 2, update DAC 2 on CS rising edge
46、1 0 0 1 1 0 Write DAC 3, update DAC 3 on CS rising edge 1 0 0 1 1 1 Write DAC 4, update DAC 4 on CS rising edge Write mode instruction set for writing to a single DAC SB RD/ WR G U Description Bit # 1 Bit # 2 Bit # 3 Bit # 4 1 0 1 0 Write all DACs, no update of DAC outputs 1 0 1 1 Write all DACs, up
47、date all outputs on CS rising edge Write mode instruction set for writing to all DACs FIGURE 2. Mode selection tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95512 DEFENSE SUPPLY CENTER COLUMBUS COLU
48、MBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 SB RD/ WR G R/ F M/L A1 A0 Description Bit # 1 Bit # 2 Bit # 3 Bit # 4 Bit # 5 Bit # 6 Bit # 7 1 1 0 0 0 0 0 Read DAC 1, LSB first, data changes on the falling edge 1 1 0 0 0 0 1 Read DAC 2, LSB first, data changes on the falling edge 1 1 0 0 0 1 0 Read DAC 3, LSB first, data changes on the falling edge 1 1 0 0 0 1 1 Read DAC 4, LSB first, data changes on the falling edge 1 1 0 0 1 0 0 Read DAC 1, MSB first, data changes on the falli
