1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added case outline “Y“. Updated boilerplate 97-03-18 Raymond Monnin B Boilerplate update and part of five year review. tcr 06-04-04 Raymond Monnin REV SHET REV B B B B B B B B B B B B B B B B B B SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
2、 30 31 32 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR
3、 USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 95-09-19 MICROCIRCUIT, MEMORY, DIGITAL, 1K X 36 DUAL PORT CLOCKED FIFO, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-95608 SHEET 1 OF 32 DSCC FORM 2233 APR
4、97 5962-E295-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95608 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing d
5、ocuments three product assurance class levels consisting of space application (device class V), high reliability (device classes M and Q), and nontraditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifyi
6、ng Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment. 1.2 PIN. The PIN is as shown in the following example: 1.2.1 RHA design
7、ator. Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-)
8、 indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 ACT3641 1K X 36 clocked FIFO 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance
9、level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A N Certification and qualification to MIL-PRF-38535 with a non-traditional perfo
10、rmance environment (encapsulated in plastic) 1/ Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 120 Plastic quad flat pack
11、age Y See figure 1 132 Ceramic quad flat package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes N, Q and V or MIL-PRF-38535, appendix A for device class M. 1.2.5.1 Lead finish D or E. Lead finishes D or E shall be designated by a single letter as follows: Fini
12、sh letter Process D Palladium E Gold Flash Palladium 1/ The manufacturer has the option of supplying lead finish D or E. 5962 - 95608 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (s
13、ee 1.2.3) / Drawing number Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95608 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ra
14、tings. 2/ 3/ 4/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (I/O ports) (VIN). -0.5 V dc to VCC+ 0.5 V dc 5/ DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc 5/ DC output current (IO) (per output)(VO= 0.0 V to VCC) . 50 mA DC input clamp current (IIK) (VINVCC)
15、 . 20 mA DC output clamp current (IOK) (VOUTVCC) 50 mA Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds). +300C Thermal resistance, junction-to-case (JC). 3.3C/W Junction temperature (TJ) +175C Maximum power dissipation (PD) . 314 mW 6/ VCCcurrent (IVCC) . 400
16、 mA Ground current (IGND) . 400 mA 1.4 Recommended operating conditions. 3/ 4/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Maximum low level input voltage (VIL) +0.8 V Minimum high level input voltage (VIH). +2.0 V Maximum high level output current (IOH) -4.0 mA Maximum low level output curren
17、t (IOL) +8.0 mA Case operating temperature range (TC). -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issue
18、s of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard
19、 Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from th
20、e Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ Unless otherwise n
21、oted, all voltages are referenced to GND. 4/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 5/ The input negative voltage rating may be exceeded provided that the input clamp current rating is observed. 6/ Powe
22、r dissipation values are derived using the formula PD= VCCICC+ nVOLIOL, where VCCand IOLare as specified in 1.4 above, ICCand VOLare as specified in table I herein, and n represents the total number of outputs. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
23、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95608 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this draw
24、ing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with MIL-PRF-38535 and as s
25、pecified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-
26、JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes N, Q, and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 C
27、ase outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table(s) shall be as specified on figure 3. 3.2.4 Block or logic diagram(s). The block or logic di
28、agram(s) shall be as specified on figure 4. 3.2.5 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figures 5 and 6 respectively. 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as specified when available. 3.3 Electrica
29、l performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requi
30、rements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where ma
31、rking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q and V shall be in accordance with MIL-PR
32、F-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes N, Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required
33、 in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes N, Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance s
34、hall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for d
35、evice classes N, Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95608 DE
36、FENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits 3/ Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A Subgroups 2/ Min Max Unit Hi
37、gh level output voltage VOHFor all inputs affecting output under test, VIN= 2.0 V or 0.8 V,IOH= -4.0 mA, VCC= 4.5 V 01 1, 2, 3 2.4 V Low level output voltage VOLFor all inputs affecting output under test, VIN= 2.0 V or 0.8 V,IOL= 8 mA, VCC= 4.5 V 01 1, 2, 3 0.5 V Input current II 4/ For input under
38、test, VI= VCCor GND, VCC= 5.5 V 01 1, 2, 3 5 A Three-state output leakage current high IOZH5/ For control input affecting output under test, VIN= 2.0 V or 0.8 V,VOUT= VCC, VCC= 5.5 V 01 1, 2, 3 5 A Three-state output leakage current low IOZL5/ For control input affecting output under test, VIN= 2.0
39、V or 0.8 V,VOUT= GND, VCC= 5.5 V 01 1, 2, 3 -5 A Quiescent supply current, outputs high ICCFor all inputs, VIN= VCC-0.2 V or GND IOUT= 0 A, VCC= 5.5 V Output = port B 01 1, 2, 3 400 A CSA = 0.8 V A0-A35 CSB = 0.8 V B0-B35 Quiescent supply current delta, TTL input level ICC 6/ For input under test, V
40、IN= 3.4 V For all other inputs VIN= VCCor GND, VCC= 5.5 V All other inputs 01 1, 2, 3 1 mA Input capacitance CINControl inputs 4 4 I/O capacitance CI/OTC= +25C, VBIAS= 0 V VCC= 5.0 V, See 4.4.1b A or B ports 01 4 8 pF Functional tests 7/ VIH= 2.0 V, VIL= 0.8 V, verify output VO, VCC= 4.5 V and 5.5 V
41、, 4.4.1c 01 7, 8A, 8B L H Clock frequency CLKA or CLKB fclock01 9, 10, 11 50 MHz Clock cycle time CLKA or CLKB tc01 9, 10, 11 20 Pulse duration, CLKA and CLKB high or low tw01 9, 10, 11 8 Setup time, A0-A35before CLKA, and B0-B35before CLKB tsu(D)01 9, 10, 11 6 Setup time, ENA to CLKA and ENB to CLK
42、B tsu(EN1)CL= 20 pF minimum, VCC= 4.5 V and 5.5 V, See figures 5 and 6 as applicable 01 9, 10, 11 6 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95608 DEFENSE SUPPLY CENTE
43、R COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits 3/ Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A subgroups 2/ Min Max Unit Setup ti
44、me, CSA and MBA to CLKA and CSB , W /RB, and MBB to CLKB tsu(EN2)01 9, 10, 11 7.5 Setup time, W/ R A to CLKA tsu(EN2)01 9, 10, 11 9.0 Setup time, RTM and RFM to CLKB tsu(RM)01 9, 10, 11 6.5 Setup time, RST low before CLKA or CLKB tsu(RS)8/ 01 9, 10, 11 6 Setup time, FS0 and FS1 before RST high tsu(F
45、S)01 9, 10, 11 10 Setup time, FS0/SD before CLKA tsu(SD)9/ 01 9, 10, 11 6 Setup time, FS1/ SEN before CLKA tsu(SEN)9/ 01 9, 10, 11 6 Hold time, A0-A35 after CLKA and B0-B35 after CLKB th(D)01 9, 10, 11 0 Hold time, ENA after CLKA and ENB after CLKB th(EN1)01 9, 10, 11 0 Hold time, CSA , W/ R A, and
46、MBA after CLKA and CSB , W /RB, and MBB after CLKB th(EN2)01 9, 10, 11 0 Hold time, RTM and RFM after CLKB th(RM)01 9, 10, 11 0 Hold time, RST low after CLKA or CLKB high th(RS)8/ 01 9, 10, 11 6 Hold time, FS0 and FS1 after RST high th(FS)CL= 20 pF minimum, VCC= 4.5 V and 5.5 V, See figures 5 and 6
47、as applicable 01 9, 10, 11 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95608 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM
48、 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits 3/ Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A subgroups 2/ Min Max Unit Hold time, FS1/ SEN high after RST high th(SP) 9/ 01 9, 10, 11 0 Hold time, FS0/SD after CLKA th(SD) 9/ 01 9, 10, 11 0 Hold time, FS1/ SEN after CLKA th(SEN) 9/ 01 9, 10, 11 0 Skew time, between CLKA and CLKB for OR and IR tsk(1)10/ 01 9, 10, 11
