1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. Update radiation hardness assurance boilerplate paragraphs. Add appendix A to document. LTG 07-07-18 Thomas M. Hess B Correct die feature (backside metallization to GOLD) in figure A-1 of appendix
2、 A. Update boilerplate paragraphs to current MIL-PRF-38535 requirements. MAA 10-03-26 Thomas M. Hess REV SHET REV B B B B B B B B B B B B B B B B SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A
3、 PREPARED BY Thomas M. Hess DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas M. Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, RADIATION HARDENED CMOS STATI
4、C CLOCK CONTROLLER/GENERATOR, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-01-05 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-95820 SHEET 1 OF 30 DSCC FORM 2233 APR 97 5962-E217-10 Provided by IHSNot for ResaleNo reproduction or networking permitted
5、without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95820 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device cl
6、asses Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in t
7、he following example: 5962 R 95820 01 V X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the
8、MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device
9、 type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 82C85RH Radiation Hardened, CMOS static clock controller/generator 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Devic
10、e class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are
11、 as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line X CDFP4-F24 24 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A f
12、or device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95820 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1
13、/ Supply voltage (VDD) . +6.5 V dc Input, output or I/O voltage range . GND -0.3 V dc to VDD+0.3 V dc Storage temperature range (TSTG) -65C to +150C Junction temperature (TJ) . +175C Lead temperature (soldering 10 seconds) +300C Thermal resistance junction-to-case (JC): Case outline J 12C/W Case out
14、line X 10C/W Thermal resistance junction-to-ambient (JA): Case outline J 52C/W Case outline X 70C/W Maximum package power dissipation at TA= 125C (PD) 2/: Case outline J 0.96 W Case outline X 0.71 W 1.4 Recommended operating conditions. 2/ 3/ Operating supply voltage range (VDD) . +4.5 V dc to +5.5
15、V dc Operating temperature range (TA) . -55C to +125C Input low voltage range (VIL) . 0.0 V dc to +0.8 V dc Input high voltage range (VIH) . 3.5 V dc to VDDReset input high voltage range (VIH) . 3.5 V dc to VDD1.5 Radiation features. Maximum total dose available (dose rate = 50-300 rads(Si)/s) . 100
16、 krads(Si) Dose rate upset. 108rad(Si)/s 3 Single event phenomenon (SEP): Effective linear energy threshold (LET): Single event upset 3/ 4/ Single event latchup 3/ 4/ _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels ma
17、y degrade performance and affect reliability. 2/ If device power exceeds package dissipation capability provide heat sinking or derate linearly (derating is based on JA) at a rate of 19.2 mW/C for case J, 14.3 mw/C for Case X. 3/ Limits are guaranteed by design or process, but not production tested
18、unless specified by the customer through the purchase order or contract. 4/ Value to be added when testing is completed. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95820 DEFENSE SUPPLY CENTER COLUMBUS CO
19、LUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the iss
20、ues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standar
21、d Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document
22、Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the soli
23、citation or contract. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM F1192- Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Copies of this document is available online at http:/www.astm.org/ or from ASTM Internati
24、onal, P. O. Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable la
25、ws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) pl
26、an. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.1.1 Microcircuit die. For the re
27、quirements of microcircuit die, see appendix A to this document. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class
28、M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Timing waveforms and load circuit. The timing wa
29、veforms and load circuit shall be as specified on figure 3. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-
30、95820 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter l
31、imits are as specified in table IA and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The par
32、t shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product usin
33、g this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q an
34、d V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in o
35、rder to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA pr
36、ior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance.
37、 A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC
38、-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers f
39、acility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, app
40、endix A) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95820 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characte
41、ristics. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage, CLK or CLK50 VOH1VDD= 4.5 V, IOH= -5.0 mA VIN= 0 V or 4.5 V 1, 2, 3 All VDD-0.4 V High level output voltage VOH2VDD= 4.5 V, IOH= -2.5 mA VIN= 0 V or
42、 4.5 V 1, 2, 3 All VDD-0.4 V Low level output voltage VOLVDD= 4.5 V, IOL= +5.0 mA VIN= 0 V or 4.5 V 1, 2, 3 All 0.4 V Input leakage current, high or low IIL, IIHVDD= 5.5 V VIN= 0 V or 5.5 V Input pins except: 11 to 15, 21, 23 1, 2, 3 All -1.0 +1.0 A Bus hold leakage current, high 2/ IBHHVDD= 4.5 V,
43、5.5 V VIN= 3.0 V, Pins: 11 to 15, 21 1, 2, 3 All -200 -20 A Standby power supply current IDDSBVDD= 5.5 V, VIN= GND or VDDIO= 0 mA 1, 2, 3 All 100 A Operating power supply current IDDOPVDD= 5.5 V, VIN= GND or VDDIO= 0 mA Crystal frequency = 15 MHz 1, 2, 3 All 80 mA RESET input hysteresis 3/ (+)VT, (-
44、)VTVDD= 4.5 V and 5.5 V 1, 2, 3 All 0.25 V Input capacitance CINf = 1 MHz, VDD= Open See 4.4.1c 4 All 5 pF Output capacitance COUT4 All 15 pFFunctional tests VDD= 4.5 V and 5.5 V VIN= GND or VDDf = 1 MHz, See 4.4.1b 7, 8 All Noise immunity functional test VDD= 5.5 V VIN= GND or 3.5 V and VDD= 4.5 V
45、VIN= 0.8 V or VDDSee 4.4.1b 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95820 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC
46、 FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max TIMING REQUIREMENTS External frequency high time tEHEL 90% to 90%VINVDD= 4.5 V, See figure 3 9, 10, 11 All
47、 25 ns External frequency low time tELEH10% to 10%VINVDD= 4.5 V, See figure 3 9, 10, 11 All 25 ns RES or START valid to CLK low 3/ tSTARTVDD= 4.5 V and 5.5 V See figure 3 9, 10, 11 All 2TELEL+3 ns STOP command valid to CLK high 3/ tSTOPVDD= 4.5 V and 5.5 V See figure 3 9, 10, 11 All 2TCLCL+3 3TCHCH+
48、55 ns EFI or crystal period tELELVDD= 4.5 V, See figure 3 9, 10, 11 All 65 ns External frequency input duty cycle tEFIDC9, 10, 11 All 45 55 % Crystal frequency 4/ f 9, 10, 11 All 2.4 15 MHz RDY1, RDY2 active setup to CLK tR1VCLASYNC = high VDD= 4.5 V, See figure 3 9, 10, 11 All 55 ns RDY1, RDY2 active setup to CLK tR1VCHASYNC = low VDD= 4.5 V, See figure 3 9, 10, 11 All 55 ns RDY1, RDY2 inactive setup to CLK tR1VCLVDD= 4.5 V, See figure 3 9, 10, 11 All 55 ns RDY1, RDY2 hold to CLK tCLR1X VDD= 4.5 V, See figure 3 9, 10, 11
