1、SMD-5962-95837 999999b 008L988 5LT LTR DESCRIPTION DATE W.MO-DA) APPROVED REV SHEET REV SHEET I 15 I 16 I 17 REV STATUS OF SHEETS PMIC NIA STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA REV 111 SHEET PREPARED BY T
2、homas M. Hess CHECKED BY Thomas M. Hess APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 95-11-22 REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL, 32-BIT RISC MICROPROCESSOR, 3.3 V, JTAG, MONOLITHIC SILICON SIZE I CAiYiOE8 I 5962995837 A SHEET I OF 26 ES
3、C FORM 193 JUL 94 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-El 91 -96 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-95837 = 999999b 008l1989 456 = STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONI
4、CS SUPPLY CENTER DAYTON, OHIO 45444 1. SCOPE 1.1 a. This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Three product assurance classes consisting of space application (device class V), military high reliability (device classes M and 9). and non-tradition
5、al military (device class N) with a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class E microcircuits in accordance with 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883
6、in conjunction with comp1iant non-JAN devices“. the application environment. When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for 1.2 m. The PIN shall be as shown i.n,the
7、 following example: 95837 Federa 1 RHA $“ILL Devi ce Devi ce Case Lead 11 stock class designator trie class outline finish designator (see 1.2.1) / Drawing nunber (see 1.2.2) des i gnator (see 1.2.4) (see 1.2.5) / (see 1.2.3) 1.2.1 RHA desianator. Device classes N, Q, and V RHA marked devices shall
8、meet the MIL-1-38535 specified RHA 1.2.2 Device tme(s.1. The device type(s) shall identify the circuit function as follows: levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. Device tme Generic number Circuit function Temerature ranae o1 80486DX4 3
9、2-bit microprocessor -55.C to 125C 75 MHz 02 80486DX4 32-bit microprocessor -5PC to 1250C 100 MHz 03 80486DX4 32-bit microprocessor -40eC to 125C 75 MHz 04 80486DX4 32-bit microprocessor -4OC to 125C 100 MHz 05 80486DX4 32-bi t microprocessor -4PC to llPC 75 MHz 06 80486DX4 32-bit microprocessor -40
10、-C to llOC 100 MHz SIZE A 5962-95837 REVISION LEVEL SHEET 2 1.2.3 Device class desianator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device reau irements documentat ion M N Vendor self-certif ication to the requirements for
11、non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 l/ Certification and qualification to MIL-1-38535 with a non-traditional performance environment 2/ Q or V Certification and qualification to MIL-1-38535 1.2.4 Case outlines). The case outline(s) shall be as designated in MIL-STD-
12、1835 and as follows: Out1 ine letter Descri Dt ive des ianator Termi na 1 s Packaae stvle X Y CMGA9-Pl68 See Figure 1 168 Ceramic, pin grid array 196 Leaded chip carrier with unformed 1 eads 1.2.5 Lead finish. The lead finish shall be as specified in MIL-1-38535 for device classes N, Q, and V. Finis
13、h letter “X“ shall not be marked on the microcircuit or its packaging. The “X“ designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference. L/ For this drawing device class M shall not apply. - 2/ Any device outside the tra
14、ditional performance environment (i.e., an operating temperature range of -55C to t125C and which requires hermetic packaging). 8 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SHD-59b2-95837 W 999999b OOB1990 178 W SIZE A STAN
15、DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 1.3 Absolute maximm ratinqs .u Storage temperature range . Supply voltage with respect to ground range . Voltage on any pin with respect to ground range Maximm power dissipation (PD) Lead temperature (solde
16、ring, 10 seconds) Thermal resistance, junction-to-case (BJC): . Case X . Case Y . Maxim junction temperature (TJ) . 1.4 in. 5962-95837 SHEET 3 . -65% to +150C . Vc . 0.5 V to +4.6 V . -0.5 V to Vcc + 0.5 V . 5u . 3DOC . See MIL-STD-1835 . 2.5C/U . 150C Case operating temperature range See 1.2.2 Supp
17、ly voltage, (VCC) 3.3 V i5% 1.5 Diaital loaic test ina for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) 98.5 percent 2. APPLICABLE DOCUMENTS 2.1 Govermient stxc ification. standards. bullet in. and handbook. Unless otherwise specifie
18、d, the following specification, standards, bulletin, and handbaok of the issue listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. SPECIFICATION MI LI TARY MIL-1-38535 - Int
19、egrated Circuits, Manufacturing, General Specification for. STANDARDS MI LI TARY MIL-STD-883 - Test Methods and Procedures for Microelectronics. MIL-STD-973 - Configuration Management MIL-STD-1835 - Microcircuit Case Outlines. BULLETIN MILITARY MIL-BUL-103 - List of Standardized Military Drawings (S
20、MDIS). HANDBOOK MIL I TARY MIL-HDBK-780 - Standardized Military Drawings. (Copies of the specification, standards, bulletin, and handbook required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting act
21、ivity.) 1/ Stresses above the absolute maximm rating may cause permanent damage to the device. Extended operation at the maxim levels may degrade performance and affect reliability. - DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-
22、,-,- 2.2 Qee figure 4 9.10.11 01.03.05 02.04 ,O6 14 11 ns System clock fall time S/ t4 2.0 V to 0.8 V iee figure 4 9,10,11 01,03 ,O5 02,04 ,O6 4 3 ns System clock rise time B/ t5 0.8 V to 2.0 V ;ee figure 4 9,10,11 01,03 ,O5 02 ,O4 ,O6 4 3 ns mA31 ,PWT, PCD, BEO-3#,M/IO# I D/C#, WIR# ,ADS#,LOCK#, FE
23、RR#,BREQ,HLDA VALID DELAY, CACHE#, HITM# t6 iee figure 4 9,10,11 01,03,05 02.04.06 19 14 ns 2 2 jee figure 4 81 9.10.11 O1 .O3 ,O5 02,04 ,O6 28 20 t7 ns A2-A31 ,PWT , PCD, BEO-3# ,M/IO#, D/C#,W/R#,ADS#.LOCK# FLOAT DELAY ,CACHE# See footnotes at end of tablc t I 5962-95837 STANDARD MICROCIRCUIT DRAWI
24、NG DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I SHEET REVISION LEVEL DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SUD-5962-95837 9999996 0081994 813 Group A subgroups Device type 9,10,11 01,03,05 02,04,06 9,10,11 01
25、,03,05 02,04,06 9,10,11 01,03,05 02,04,06 9,10,11 01,03,05 02,04,06 9,10,11 01,03,05 02,04,06 9,10,11 01,03,05 02,04,06 9,10,11 01,03,05 02,04,06 9,10,11 01,03,05 02,04,06 9,10,11 01,03,05 02 I 04,06 9, IO, 1 1 O1 I 03,05 02,04,06 9,10,11 01,03,05 02,04,06 TABLE I. f m. h Unit I Conditions 1/ -55C T
26、C +125C unless otherwise specified Limits Test Min Max 5ee figure 4 24 14 CHK# VALID DELAY t8 ns 2 2 - 2 2 - 2 2 - 8 5 3 3 8 5 - 3 3 - 8 5 - 3 3 - See figure 4 24 14 ;LAST#, PLOCK#, SMIACT# Valid delay t8a ns ;LAST#, PLOCK# FLOAT DELAY See figure 4 u 28 20 ns t9 I See figure 4 20 14 ns iO-D31,DPO-3
27、WRITE DATA VALID DELAY t10 See figure 4 28 20 ns io-031 ,DPO-3 WRITE DATA FLOAT DELAY 8/ tl1 See f igure 4 ns t12 :ADS#, INV SETUP TIME I !ADS#, INV HOLD TIME See figure 4 ns t13 :EN#, BS16#, BS8#, UB/UT# setup time t14 See figure 4 ns :EN#,BS16#,BS8#, WUT# setup time t15 See figure 4 ns t16 See fig
28、ure 4 ns tDY#,BRDY# SETUP TIME ns t17 See figure 4 IDY#,BRDY# HOLD TIME I See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 5962-95837 SHEET 7 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted wi
29、thout license from IHS-,-,-TAB1 9,l O , 1 1 Test O1 , 03,05 02,04,06 HOLD,AHOLD SETUP TIME See figure 4 See figure 4 t18 9,10,11 01,03,05 02,04,06 9,10,11 01,03,05 O? 04.06 BOFF# SETUP TIME RESET, FLUSH#, A20M#,NMI, INTR, IGNNE#, SRESET, STPCLK#,SMI# HOLD TIME 1 t18a t2l HOLD,AHOLD,BOFF# HOLD TIME 9
30、,10,11 1 01,03,05 02 , 04,06 I t20 RESET, FLUSH#, A20M#,NMI, INTR,IGNNE#, SRESET, STPCLK#, SMI# setup time I 1 t22 DO-D31 ,DPO-3,A4-A31 READ SETUP TIME DO-D31 ,DPO-3,A4-A31 READ HOLD TIME I JTAG le/ TCK frequency I t24 TCK period fjb TCK high time 1 TCK low time fs(l TCK rise time e TCK fall time Se
31、e footnotes at end of table. E I. Electrical e rformance characteristics. I I Conditions 1/ -55C i TC i +125C I unless otherwise specified See figure 4 See figure 4 W 9,10,11 01,03,05 1 Io2,04.06 I e/ See figure 4 1 9,l O, 1 1 102.0406 01,03 , 05 I I I I See figure 4 9,10,11 01,03,05 I 102,W,M I I I
32、 I See figure 4 . I I 1X clock See figure 5 See figure 5 9,10,11 I I VIN 2.0 V 9,10,11 ALL See figure 5 VI = 0.8 V 9,10,11. ALL see Yigure 5 0.8V L V i 2.0V see figure! 2.0V i VI i 0.8V See figure ! I 9,10,11 1 All Limits Unit I I 25 1 MHz 5962-95837 REVISION LEVEL STANDARD MICROCIRCUIT DRAWING DEFE
33、NSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 I I DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SUD-5962-95837 9999996 0083996 696 ievi ce Limits type Min Max . TABLE I. Flectrical wrformance Characteristics. Unit Test SWL Con
34、ditions 1/ Group A -55C s TC a +125C unless otherwise specified subgroups TDI, TMS Setup time TDI, TMS hold time TDO valid delay TDO float delay All outputs (non-test) valid delay t30 See figure 5 9,10,11 t31 See figure 5 9,10,11 t3* See figure 5 9,10,11 t33 See figure 5 9,10,11 9,10,11 Al 1 Al 1 Al
35、 1 Al 1 Al 1 a ns 7 ns 3 25 ns 30 ns 3 25 ns All outputs (non-test) float delay Al1 inputs (non-test) setup time All inputs (non-test) hold time t35 See figure 5 9,10,11 t36 See figure 5 9,10,11 t37 See figure 5 9,10,11 1/ All testing to be performed using worst-case test conditions unless otherwise
36、 specified. specifications assune CL = 50 pF. u Actual value tested may vary due to test hardware limitations, however, specified value is guaranteed. u Parameter is for input pins with internal putldown resistors. I/ Parameter is for input pins with internal pullup resistors. All timing u This para
37、meter is for proper power supply selection. 3.465 V. It is measured using the uorst-case instruction mix at Vcc = 4/ The I stop grant specification refers to the Icc value once the device enters the stop grant or halt auto pouerkn state. The Icc stop clock specification refers to the lCc value once
38、the device enters the stop clock state. VIL must be equal to Vcc and OV, respectively, in order to meet the Icc stop clock specifications. 8/ Guaranteed by design characterization but not tested. e/ A reset pulse width of 15 CLK cycles is required for warm resets (RESET or SRESET). restes) require R
39、ESET to be asserted for at least lms after Vcc and CLK are stable. 1p/ Test pins (TCK, TDI, TDO, TMS) are exceptions. VIH and Power-up resets (cold These pins are tested and guaranteed to the following limits: VIL = o v VI“ = 3 v VOL = VOH = 1.5 v IOL = IOH 0 t STANDARD MICROCIRCUIT DRAWING DEFENSE
40、ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 1 5962-95837 I SHEET REVISION LEVEL DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5762-95837 7799996 0083997 522 Case Y Il 164 PLCS REF ETAIL A PFTAIL B SEATING AND BASE PLANE c
41、* .o35 a.003 14 PLCSI 14 PLACES) Inches .O03 .O05 . O10 . o12 . O20 .O25 . O30 .O35 . o45 .O50 . O60 .O66 .O60 .O94 -247 FIGURE 1. Case outlk. REF mm O. 08 O. 13 O. 25 0.30 0.51 O. 64 0.76 0.89 1.14 1.27 1.52 1.68 2.03 2.39 6.27 STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER I I I
42、5962-95837 I DAYTON, OHIO 45444 I K=V3uN * DESC FORM 19% JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95833 999999b 0083998 4b9 U S ST Issue . 1 96 1 96 1.270 2.03 Reference O. O50 O. O80 Reference 1.14 1.93 Reference 0.045 O. O76
43、Reference IUS 7/90 Case Y FIGURE 1. Case outline - Continued. 5962-95837 REVISION LEVEL STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DATON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S R O P N
44、n L K J H G F E D C B A SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Case X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 5962-95837 REVISION LEVEL SHEET 12 A27 At6 O0 A28 A25 O0 A31 ss O0 O0 A29 O0 02 O1 O0 O0 SS 06 O0 O0 O0 O0 O0 OP1 08 O0 O0 O9 O13 O0 Oll
45、O18 O0 o19 021 O0 DL0 022 vss vcc vss vcc vcc5 0s vss 03 vss vcc vss vcc A23 VOLOET A14 O00 O00 A17 Al9 A21 O00 A30 O OP0 O 04 O O7 O O14 O 016 O OP2 O Olt O O15 O O10 O 017 O vcc vss A18 CLK vcc vcc O00 vss vss vss O00 TCK O23 OP3 vss vcc O O A2 4 O 027 O 025 O 024 A12 O A15 O A22 O 026 O O vcc vss
46、 vss vcc O O A2 O O 028 O 031 O o29 Vss Vss Vss Vss A10 Vss A6 A4 AO9 000000000 vcc vcc vcc All A8 vcc A3 BLAST. CLKHUL 000000000 A16 A13 A9 AS A7 A2 BREO PLOCK= PCHK= 000000000 HLOA cc ss O00 LOCK. WlO= WR= O00 O00 O00 BEO. vcc vss O00 BE2= BEl+ PCD O00 BROY. vcc vss O00 STPCLK. cc ss O00 KEN= ROY=
47、 BE38 O00 HOLD vcc vss O00 AZOM BSB+ BOFF= O00 NC FERR. FLUSHm RESET BS168 000000000 cc cc CACHE, bJwwTi Tils Nil1 TOO EADS. 000000000 SS INV ss HITH8 INC TOI ICNNE=JNTR AHOLO o/c= vcc vss vcc vss cc SHIACT. 00000000000000000 S R O P N n L K J H t F E O C B A 1 2 3 4 5 6 7 B 9 10 11 12 13 14 15 16 1
48、7 Note: lhe 5 Volt reference voltage input pin (Vcc5)-is the reference voltage for the 5v-tolerant 1/0 buffers. This signal should be connected to the +5 V 15% for use with 5 V system logic, If all inputs to the device are from 3 V system logic this pin should be connected to 3.3 V t5%. # indicates
49、active low signal. FIGURE 2. ferm inal connectiom. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-75837 m 9999996 0082000 715 m SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL a 5962-95837 SHEET 13
