1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add truth table and delete 1.5. Make changes to 4.4.1b and 4.4.1c. Replace reference to MIL-STD-973 with reference to MIL-PRF-38535. - ro 06-05-01 R. MONNIN REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6
2、7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY TUAN NGUYEN DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY LARRY SHAW COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY RAYMOND MONNIN AND AGENCIES OF THE DEPARTMENT OF
3、DEFENSE DRAWING APPROVAL DATE 97-05-30 MICROCIRCUIT, DIGITAL, BIPOLAR, SYNCHRONOUS 4-BIT COUNTER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-97548 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E286-06 Provided by IHSNot for ResaleNo reproduction or networking permitted witho
4、ut license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97548 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes
5、 Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the fo
6、llowing example: 5962 - 97548 01 Q C X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-
7、PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device typ
8、e(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54163 Synchronous 4-bit counter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentati
9、on M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as f
10、ollows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 2 CQCC1-N20 20 Leadless square chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-3
11、8535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97548 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute
12、maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc Input voltage (VIN) -0.5 V dc to +5.5 V dc Interemitter voltage 2/ . 5.5 V Operating free air temperature range . -55C to +125C Maximum power dissipation (PD) . 500 mW Storage temperature range -65C to +150C Thermal resistance, ju
13、nction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175 C 1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.5 V dc to 5.5 V dc High-level output current (IOH) . -800 A max Low-level output current (IOL) 16 mA max Clock frequency, (fclock) . 25 MHz max Width of clock pu
14、lse, tw(clock) . 25 ns min Width of clear pulse, tw(clear) 20 ns min Setup time, tsu, from data inputs A, B, C, D to CLK input 3/ 20 ns min Setup time, tsu, from ENP to CLK input 3/ 20 ns min Setup time, tsu, from LOAD to CLK input 3/ . 25 ns min Setup time, tsu, from CLR to CLK input 3/ 20 ns min H
15、old time at any input, th. 0 ns min Operating free-air temperature range (TA) . -55 C to +125 C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless oth
16、erwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-ST
17、D-1835 - Interface Standard Electronic Component Case Outlines. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ This is the voltage between two emitters of a multiple
18、-emitter transistor. 3/ The waveforms on tsuare on figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97548 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2
19、234 APR 97 DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document
20、 Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws a
21、nd regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan.
22、The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical
23、 dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein . 3.2.2 Terminal conne
24、ctions. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 3. 3.3 Electrical performance characteristics
25、 and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test
26、requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN n
27、umber is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device clas
28、s M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6
29、Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer i
30、n order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirement
31、s of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided wit
32、h each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. Provided by IHSNot
33、for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97548 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditio
34、ns -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max High-level input voltage VIH1, 2, 3 01 2 V Low-level input voltage VIL1, 2, 3 01 0.8 V Input clamp voltage VIKVCC = 4.5 V, II= -12 mA 1, 2, 3 01 -1.5 V High level output voltage VOHVCC = 4.5 V, VIH= 2 V, VI
35、L= 0.8 V, IOL= -800 A 1, 2, 3 01 2.4 V Low-level output voltage VOLVCC = 4.5 V, VIH= 2 V, VIL= 0.8 V, IOL= 16 mA 1, 2, 3 01 0.4 V Input current at maximum input voltage IIVCC = 5.5 V, VI= 5.5 V 1, 2, 3 01 1 mA High-level input current IIHVCC = 5.5 V, CLK or ENT 1, 2, 3 01 80 A VI= 2.4 V Other inputs
36、 1, 2, 3 40 Low-level input current IILVCC = 5.5 V, CLK or ENT 1, 2, 3 01 -3.2 mA I= 0.4 V Other inputs 1, 2, 3 -1.6 Short-circuit output current IOS1/ VCC = 5.5 V 1, 2, 3 01 -20 -57 mA Supply current, all outputs high ICCH2/ VCC = 5.5 V 1, 2, 3 01 85 mA Supply current, all outputs low ICCL3/ VCC =
37、5.5 V 1, 2, 3 01 91 mA Functional test 4/ VIN = VIHmin or VILmax verify output VO, see 4.4.1b 7, 8 01 Maximum clock frequency fmaxCL= 15 pF, RL= 400 , see figure 3 5/ 9 01 25 MHz tPLH9 01 35 ns Propagation delay time from CLK to RCO tPHL35 tPLH9 01 20 ns Propagation delay time from CLK ( LOAD input
38、high ) to any Q tPHL23 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97548 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR
39、 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxtPLHCL= 15 pF, RL= 400 , see figure 3 5/ 9 01 25 ns Propagation delay time from CLK ( LOAD input low ) to any Q tPHL9 29 tPL
40、H01 16 ns Propagation delay time from ENT to RCO tPHL9 16 Propagation delay time from CLR to any Q tPHL01 38 ns 1/ Not more than one output should be shorted at a time. 2/ ICCHis measured with the load input high, then again with the load input low, with all other inputs high and all outputs open. 3
41、/ ICCLis measure with the clock input high, then again with the clock input low, with all other inputs low and all outputs open. 4/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. The test v
42、ectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. Functional tests shall be performed in sequence as approved by t
43、he qualifying activity on qualified devices. Allowable tolerances per MIL-STD-883 may be incorporated. For outputs, L 0.8 V, H 2.0 V. 5/ Propagation delay for clearing is measured from the clock input transition. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent,
44、and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this
45、 drawing shall be in microcircuit group number 5 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97548 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL
46、A SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines E, F 2 Terminal number Terminal symbol 1 CLR NC 2 CLK CLR 3 A CLK 4 B A 5 C B 6 D NC 7 ENP C 8 GND D 9 LOAD ENP 10 ENT GND 11 QDNC 12 QCLOAD 13 QBENT 14 QAQD15 RCO QC16 VCCNC 17 - - - QB18 - - - QA19 - - - RCO 20 - - - VCCFIGURE 1. Termina
47、l connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97548 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 INPUTS OUTPUTS Function CLR CLK ENP
48、 ENT LOAD A,B,C,D Qn RCO L X X X X L L Reset (clear) H X X L L L L Parallel load H X X L H H See note Parallel load H H H H X Count See note Count H X L X H X Qn See note Inhibit H X X L H X Qn L Inhibit H = High level. L = Low level. X = Dont care. H = High level one step time prior to the CLK low-to-high transition. L = Low level one setup time prior to the CLK low-to-high transition. Qn = The state of the referenced output prior to the CLK low-to-high transition. = CLK low-to-high transition. NOTE: The RCO output is high
