DLA SMD-5962-97580 REV A-2006 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL J-K POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET MONOLITHIC SILICON《可调整二重J-K阳性触发三状.pdf

上传人:orderah291 文档编号:701220 上传时间:2019-01-01 格式:PDF 页数:15 大小:98.69KB
下载 相关 举报
DLA SMD-5962-97580 REV A-2006 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL J-K POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET MONOLITHIC SILICON《可调整二重J-K阳性触发三状.pdf_第1页
第1页 / 共15页
DLA SMD-5962-97580 REV A-2006 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL J-K POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET MONOLITHIC SILICON《可调整二重J-K阳性触发三状.pdf_第2页
第2页 / 共15页
DLA SMD-5962-97580 REV A-2006 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL J-K POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET MONOLITHIC SILICON《可调整二重J-K阳性触发三状.pdf_第3页
第3页 / 共15页
DLA SMD-5962-97580 REV A-2006 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL J-K POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET MONOLITHIC SILICON《可调整二重J-K阳性触发三状.pdf_第4页
第4页 / 共15页
DLA SMD-5962-97580 REV A-2006 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL DUAL J-K POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET MONOLITHIC SILICON《可调整二重J-K阳性触发三状.pdf_第5页
第5页 / 共15页
点击查看更多>>
资源描述

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - gap 06-12-05 Raymond Monnin REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick Officer DE

2、FENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin MICROCIRCUIT, DIGITAL, BIPOLAR ADVANCED SCHOTTKY TTL, DUAL J-K POSITIVE EDGE AND AGEN

3、CIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 97-06-19 TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-97580 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E620-06 Provided by IHSNot for ResaleNo reproduction or networking perm

4、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (dev

5、ice classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as sho

6、wn in the following example: 5962 - 97580 01 Q E X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices m

7、eet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). Th

8、e device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54F109 Dual J- K positive edge triggered flip-flops with clear and preset 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as

9、 follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case

10、 outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in

11、 MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISI

12、ON LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VIN) . -1.2 V to +7.0 V 2/ Input current range (IIN) . -30 mA and +5 mA Voltage range applied to any output in the high state . -0.5 V to VCCCurrent into any o

13、utput in the low state . 40 mA Maximum power dissipation (PD) 94 mW Junction temperature (TJ) +175C Storage temperature range . -65C to +150C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.5 V to 5.5 V High-level input

14、voltage (VIH) . 2 V Low-level input voltage (VIL) 0.8 V Input clamp current (IIK) . -18 mA High-level output current (IOH) . -1 mA Low-level output current (IOL) 20 mA Case operating free-air temperature (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbook

15、s. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Man

16、ufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standar

17、d Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflic

18、t between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause perman

19、ent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ The input voltage ratings may be exceeded provided the input current ratings are observed. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I

20、HS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535

21、and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A

22、for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2

23、.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Block diagram. The block diagram shall be as specified on

24、figure 3. 3.2.5 Timing diagram. The timing diagram shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified i

25、n table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN

26、 listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designa

27、tor shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as

28、 required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirem

29、ents of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved

30、source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance

31、as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see

32、6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable require

33、d documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 3 (see MIL-PRF-38535, appendix A). Provided by IHSNot for

34、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions

35、-55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max Input clamp voltage VIKVCC= 4.5 V, II= -18 mA 1, 2, 3 -1.2 V High-level output voltage VOHVCC= 4.5 V, IOH= -1 mA 1, 2, 3 2.5 V Low level output voltage VOLVCC= 4.5 V, IOL= 20 mA 1, 2, 3 0.5 V Input current IIVCC= 5.5 V, V

36、I= 7 V 1, 2, 3 0.1 mA High level input current IIHVCC= 5.5 V, VI= 2.7 V 1, 2, 3 20 A Low level input current IILFor J, K , and CLK pins, VCC= 5.5 V, VI= 0.5 V 1, 2, 3 -0.6 mA For PRE or CLR pins, VCC= 5.5 V, VI= 0.5 V -1.8 Output short circuit 1/ current IOSVCC= 5.5 V, VO= 0 V 1, 2, 3 -60 -150 mA Su

37、pply current ICCVCC= 5.5 V 2/ 1, 2, 3 17 mA Functional test 3/ VIN= VIHmin or VILmax, verify output = VO, see 4.4.1c 7, 8 L H Clock frequency fCLK4/ 9 0 100 MHz 5/ 10, 11 0 70 Pulse duration tWCLK high, PRE or CLR low 4/ 9 4 ns CLK low 5/ 10, 11 5 Setup time, data before tSUHigh 4/ 9 3 ns CLK Low 5/

38、 10, 11 3 Setup time, inactive-state before CLK tSUPRE or CLR to CLK 4/ 5/ 6/ 9, 10, 11 2 ns Hold time, data after CLK tHHigh 4/ 5/ 9, 10, 11 1 ns Low 4/ 5/ 1 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC

39、ROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min M

40、ax Maximum frequency fMAX4/ 9 100 MHz 5/ 10, 11 70 CLK input to Q or Q output tPLH4/ 9 3 7 ns timing 5/ 10, 11 3 9 tPHL4/ 9 3.6 8 5/ 10, 11 3.6 10.5 PRE or CLR input to tPLH4/ 9 2.4 7 ns Q or Q output timing 5/ 10, 11 2.4 9 tPHL4/ 9 2.7 9 5/ 10, 11 2.7 11.5 1/ Not more than one output should be shor

41、ted at a time, and the duration of the short circuit should not exceed one second. 2/ ICCis measured with J, K , CLK, and PRE grounded then with J, K , CLK, and CLR grounded. 3/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic

42、 patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. Function tests sha

43、ll be performed in sequence as approved by the qualifying activity on qualified devices. 4/ For group A subgroup 9, VCC= 5 V, CL= 50 pF, and RL= 500 . 5/ For group A subgroups 10, 11, VCC= 4.5 V to 5.5 V, CL= 50 pF, and RL= 500 . 6/ Inactive state setup time is also referred to as recovery time. Pro

44、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines E and F 2 Terminal numbe

45、r Terminal symbol 1 1 CLR NC 2 1 J 1 CLR 3 1 K 1 J 4 1 CLK 1 K 5 1 PRE 1 CLK 6 1 Q NC 7 1 Q 1PRE 8 GND 1 Q 9 2 Q 1Q 10 2 Q GND 11 2 PRE NC 12 2 CLK 2 Q 13 2 K 2 Q 14 2 J 2 PRE 15 2 CLR 2 CLK 16 VCCNC 17 2 K 18 2 J 19 2 CLR 20 VCCNC = No connection FIGURE 1. Terminal connections. Provided by IHSNot f

46、or ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X

47、 X H See note 1 H See note 1 H H L L L H H H H L TOGGLE H H L H Q0Q0H H H H H L H H L X X Q0Q01/ The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable because it will not persist when PRE or CLR returns to its inactive (high) level. FIG

48、URE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97580 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHI

展开阅读全文
相关资源
猜你喜欢
相关搜索

当前位置:首页 > 标准规范 > 国际标准 > 其他

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1