1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - gap 02-05-20 Raymond Monnin B Boilerplate update, part of 5 year review. ksr 08-09-05 Robert M. Heber REV SHET REV B B B B B B SHEET 15 16 17 18 19 20 REV STATUS REV B B B B
2、B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED B
3、Y Raymond Monnin AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 97-06-27 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECTRICALLY ALTERABLE FLASH PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-97597 SHEET 1 OF 20 DSCC FORM 2233 APR 97 59
4、62-E516-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97597 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing docume
5、nts two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness A
6、ssurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 97597 01 Q X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawin
7、g number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA d
8、esignator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Toggle Speed (Mhz) 01 7C372i 64 Macrocell CPLD 66 02 7C372i 64 Macrocell CPLD 83 1.2.3 Device class designator. The device
9、class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Ce
10、rtification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GQCC1-J44 44 J leaded chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF
11、-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97597 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL
12、 B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -2.0 V dc to +7.0 V dc Programming supply voltage range (VPP) -2.0 V dc to +13.5 V dc 2/ DC input voltage range -2.0 V dc to +7.0 V dc 2/ Maximum power dissipation 2.5 W 3/ Lead temperature (soldering, 10
13、seconds) +260C Thermal resistance, junction-to-case (JC): Case outline X . See MIL-STD-1835 Junction temperature (TJ) +175C 4/ Storage temperature range . -65C to +150C Endurance . 25 erase/write cycles (minimum) Data retention 10 years (minimum) 1.4 Recommended operating conditions. 5/ Case operati
14、ng temperature range (TC) -55C to +125C Supply voltage relative to ground (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) 0 V dc Input high voltage (VIH) 2.0 V dc minimum Input low voltage (VIL) 0.8 V dc maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and
15、 handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circ
16、uits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780
17、- Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a
18、 part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics
19、 Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other i
20、nformational services.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Minimum dc input voltage is -0.5 V, which may overshoot to -2.0 V for periods less than 20 ns.
21、 Maximum dc voltage on output pins is VCC+ 0.5 V, which may overshoot to +7.0 V for periods less than 20 ns under load conditions. 3/ Must withstand the added PDdue to short circuit test (e.g., IOS). 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in sc
22、reening conditions in accordance with method 5004 of MIL-STD-883. 5/ All voltage values in this drawing are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97597 DEFENSE SUPPLY CENTER COL
23、UMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable law
24、s and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) pla
25、n. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physi
26、cal dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal con
27、nections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics a
28、nd postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in tabl
29、e I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the dev
30、ice. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mar
31、k for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
32、 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of complianc
33、e submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Ce
34、rtificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device clas
35、s M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to r
36、eview the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42
37、 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97597 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electri
38、cal performance characteristics. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specifiedGroup A Subgroups Device type Min Max Unit High Level output voltage VOHVCC= 4.5 V, VIL= 0.8V IOH= -2.0 mA, VIH= 2.0 V All 2.4 V Low level output voltage VOLVCC= 4.5 V, IOL= 12.0 mA
39、 VIL= 0.8 V, VIH= 2.0 V All 0.5 V High level input voltage 1/ VIHAll 2.0 7.0 V Low level input voltage 1/ VILAll -0.5 0.8 V Input leakage current IIXVCC= 5.5 V, VIN= 0 V and 5.5 V All -10 +10 A Output leakage current IOZVCC= 5.5 V, VIN= output disabled and 5.5 V All -50 +50 A Output short circuit cu
40、rrent 2/ 3/ IOSVCC= 5.5 V, VOUT= 0.5 V All -30 -160 mA Power supply current 4/ ICCVCC= 5.5 V, IOUT= 0 mA, VIN= 0 V and 5.5 V f = 1.0 MHz All 200 mA Input bus hold low Sustained current IBHLVCC= 4.5 V, VIL= 0.8 V All +75 A Input bus hold high sustained current IBHHVCC= 4.5 V, VIH= 2.0 V All -75 A Inp
41、ut bus hold low sustained overdrive current IBHLOVCC= 5.5 V All +500 A Input bus hold high sustained overdrive current IBHHOVCC= 5.5 V 1, 2, 3 All -500 A Input capacitance 2/ CIN4 All 15 pF Output capacitance 2/ COUTVIN= 5.0 V, f = 1 Mhz See 4.4.1e 4 All 5 12 pF Functional test See 4.4.1c 7,8A,8B Al
42、l 01 20 Input to combinatorial output 5/ tPD02 15 ns 01 22 Input to output through transparent input or output latch 5/ 6/ tPDL02 18 ns 01 24 Input to output through transparent input or output latches 5/ 6/ tPDLLSee figures 3 and 4 (circuit A) 9, 10, 11 02 19 ns See footnotes at end of table. Provi
43、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97597 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Conti
44、nued. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A Subgroups Device type Min Max Unit 01 24 Input to output enable 5/ 6/ tEASee figures 3 and 4 (circuit B) 9, 10, 11 02 19 ns 01 24 Input to output disable 5/ 6/ tER02 19 ns 01 5 Clock or Latch enable
45、input high time 2/ 5/ tWH02 4 ns 01 5 Clock or latch enable input low time 2/ 5/ tWL02 4 ns 01 4 Input register or latch set-up time 5/ tIS02 3 ns 01 4 Input register or latch hold time 5/ tIH02 3 ns 01 24 Input register clock or latch enable to combinatorial output 5/ tICOSee figures 3 and 4 (circu
46、it A) 02 19 ns 01 26 Input register clock or latch enable to output through transparent output latch 5/ 6/ tICOL02 21 ns 01 10 Clock or latch enable to output 5/ tCO02 8ns Register or latch data hold time 5/ tHAll 0 ns 01 10 Set-up time from input to clock or latch enable 5/ tS02 8 ns 01 20 Set-up t
47、ime from input through transparent latch to output register clock or latch enable 5/ 6/ tSL02 15 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97597 DEFENSE SUPPLY CENTER C
48、OLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specifiedGroup A Subgroups Device type Min Max Unit 01 24 Output clock or latch enable to output delay (through memory array) 5/ 6/ tCO202 19 ns 01 15 Output clock or latch enable to output clock or latch enable (through memory array) 5/ 6/ tSCS02 12 ns Hold time for input through t
