1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - gap 02-05-22 Raymond Monnin B Boilerplate update, part of 5 year review. ksr 08-09-05 Robert M. Heber REV SHET REV B B B B B B B B B SHEET 15 16 17 18 19 20 21 22 23 REV STAT
2、US REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTM
3、ENTS APPROVED BY Raymond Monnin AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 97-07-03 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECTRICALLY ALTERABLE FLASH PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-97599 SHEET 1 OF 23 DSCC FORM
4、 2233 APR 97 5962-E517-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This
5、 drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radia
6、tion Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 97599 01 Q X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see
7、1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the ap
8、propriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Toggle Speed (Mhz) 01 7C375i 128 Macrocell CPLD 66 02 7C375i 128 Macrocell CPLD 83 1.2.3 Device class design
9、ator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, app
10、endix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA7-P160 160 Pin grid array Y See figure 1 160 Quad flat package (with ring)
11、Z See figure 1 160 Quad flat package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT
12、 DRAWING SIZE A 5962-97599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -2.0 V dc to +7.0 V dc Programming supply voltage range (VPP) -2.0 V dc to +13.5 V dc 2/ DC input voltage r
13、ange -2.0 V dc to +7.0 V dc 2/ Maximum power dissipation 2.5 W 3/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Case outline X . See MIL-STD-1835 Case outline Y and Z . 7.2 C/W Junction temperature (TJ) +175C 4/ Storage temperature range . -65C to +150C En
14、durance . 25 erase/write cycles (minimum) Data retention 10 years (minimum) 1.4 Recommended operating conditions. 5/ Case operating temperature range (TC) -55C to +125C Supply voltage relative to ground (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) 0 V dc Input high voltage (VI
15、H) 2.0 V dc minimum Input low voltage (VIL) 0.8 V dc maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of the
16、se documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electro
17、nic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk
18、, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. ELECTRONICS INDUSTRIE
19、S ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to th
20、e device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Minimum dc input voltage is -0.5 V, which may overshoot to -2.0 V for periods less than 20 ns. Maximum dc voltage on output pins is VCC+ 0.5 V, which may overshoot to +7.0 V for periods less than 20
21、 ns under load conditions. 3/ Must withstand the added PDdue to short circuit test (e.g., IOS). 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 5/ All voltage values in this drawing
22、are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.3 Order of precedence.
23、In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements.
24、The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The
25、individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535
26、 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth tab
27、le shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case ope
28、rating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufac
29、turers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device c
30、lasses Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark
31、 for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For de
32、vice class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm
33、that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-P
34、RF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this
35、drawing is required for any change that may affect this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shal
36、l be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permit
37、ted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless
38、 otherwise specified Group A Subgroups Device type Min Max Unit High Level output voltage VOHVCC= 4.5 V, VIL= 0.8V IOH= -2.0 mA, VIH= 2.0 V 2.4 V Low level output voltage VOLVCC= 4.5 V, IOL= 12.0 mA VIL= 0.8 V, VIH= 2.0 V 0.5 V High level input voltage 1/ VIH2.0 7.0 V Low level input voltage 1/ VIL-
39、0.5 0.8 V Input leakage current IIXVCC= 5.5 V, VIN= 0 V and 5.5 V -10 +10 A Output leakage current IOZVCC= 5.5 V, VIN= output disabled and 5.5 V -50 +50 A Output short circuit current 2/ 3/ IOSVCC= 5.5 V, VOUT= 0.5 V -30 -160 mA Power supply current 4/ ICCVCC= 5.5 V, IOUT= 0 mA, VIN= 0 V and 5.5 V f
40、 = 1.0 MHz 250 mA Input bus hold low sustained current IBHLVCC= 4.5 V,VIL= 0.8 V +75 A Input bus hold high sustained current IBHHVCC= 4.5 V,VIH= 2.0 V -75 A Input bus hold low sustained overdrive current IBHLOVCC= 5.5 V +500 A Input bus hold high sustained overdrive current IBHLOVCC= 5.5 V 1, 2, 3 A
41、ll -500 A Input capacitance 2/ CINSee 4.4.1e 4 All 8 pF Output capacitance 2/ COUTSee 4.4.1e 4 All 5 15 pF Functional test See 4.4.1c 7, 8A, 8B All 01 20 Input to combinatorial output 5/ tPDSee figures 4 and 5 (circuit A) 9, 10, 11 02 15 ns See footnotes at end of table. Provided by IHSNot for Resal
42、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbo
43、l Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A Subgroups Device type Min Max Unit 01 22 Input to output through transparent input or output latches 5/ 6/ tPDL02 18 ns 01 24 Input to output through transparent input or output latches 5/ 6/ tPDLLSee figures 4 and 5 (circ
44、uit A) 02 19 ns 01 24 Input to output enable see figure 3 test waveforms 5/ 6/ tEASee figures 4 and 5 (circuit B) 02 19 ns 01 24 Input to output disable see figure 3 test waveforms 5/ 6/ tER02 19 ns 01 5 Clock or latch enable input high time 2/ 5/ tWH02 4 ns 01 5 Clock or latch enable input low time
45、 2/ 5/ tWL02 4 ns 01 4 Input register or latch set-up time 5/ tIS02 3 ns 01 4 Input register or latch hold time 5/ tIH02 3 ns 01 24 Input register clock or latch enable to combinatorial output 5/ tICO02 19 ns 01 26 Input register clock or latch enable to output through transparent output latch 5/ 6/
46、 tICOL02 21 ns 01 10 Clock or latch enable to output 5/ tCO02 8 ns Register or latch data hold time 5/ tHSee figures 4 and 5 (circuit A) 9, 10, 11 All 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC
47、IRCUIT DRAWING SIZE A 5962-97599 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A Subgrou
48、ps Device type Min Max Unit 01 10 Set-up time from input to clock or latch enable 5/ tS02 8 ns 01 20 Set-up time from input through transparent latch to output register clock or latch enable 5/ 6/ tSL02 15 ns 01 24 Output clock or latch enable to output delay (through memory array) 5/ 6/ tCO202 19 ns 01 15 Output clock or latch enable to output clock or latch enable (through memory array) 5/ 6/ tSCS02 12 ns Hold time for input through transparent latch from output register clock or latch enable 5/ 6/ tH
