1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added JTAG information to document. - LTG 00-03-08 Monica L. Poelking B Update boilerplate to MIL-PRF-38535 requirements. LTG 01-04-13 Thomas M. Hess C Update boilerplate to current MIL-PRF-38535 requirements. CFS 07-08-10 Thomas M. Hess D Update
2、 boilerplate to current MIL-PRF-38535 requirements. - PHN 13-05-06 Thomas M. Hess REV D D D D D D D D D D D SHEET 35 36 37 38 39 40 41 42 43 44 45 REV D D D D D D D D D D D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV D D D D D D D D D D D D D D
3、OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Larry T. Gauder DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Thanh V. Nguyen THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica L.
4、Poelking MICROCIRCUIT, DIGITAL, DIGITAL SIGNAL AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 00-01-31 PROCESSOR, MONOLITHIC SILICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-98578 SHEET 1 OF 45 DSCC FORM 2233 APR 97 5962-E389-13 Provided by IHSNot for ResaleNo reproduct
5、ion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98578 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high rel
6、iability (device classes) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as
7、 shown in the following example: 5962 - 98578 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked dev
8、ices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 320C6201B Digital signal proce
9、ssor 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated i
10、n MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 429 Ball grid array 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535. Provided by IHSNot for ResaleNo reproduction or networking
11、permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98578 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (CVDD) -0.3 V dc to +2.3 V dc Supply voltage range (DVDD) -0.
12、3 V dc to +4.0 V dc Input voltage range (VIN) . -0.3 V dc to +4.0 V dc Output voltage range (VOUT) . -0.3 V dc to +4.0 V dc Storage temperature range -55C to +150C Maximum junction temperature (TJ) +119C at 150 MHz Thermal resistance, junction-to-case (JC) 3.00C/W Solder ball reflow condition (Peak
13、temperature) . +220C 10C 1.4 Recommended operating conditions. Supply voltage range (CVDD) +1.71 V dc to +1.89 V dc Supply voltage range (DVDD) +3.14 V dc to +3.46 V dc Supply ground (VSS) . +0.0 V dc to +0.0 V dc High level input voltage (VIH) 2.0 V Low level input voltage (VIL) 0.8 V High level ou
14、tput current (IOH) . -12 mA Low level output current (IOL) 12 mA Case operating temperature range (TC) -55C to +115C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specifi
15、ed herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard
16、Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quic
17、ksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.
18、2/ All voltage values are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98578 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Gove
19、rnment publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the document(s) are those cited in the solicitation or contract. INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 - IEEE
20、Standard Test Access Port and Boundary Scan Architecture. (Copies of these documents are available online at http:/www.ieee.org or from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331). 2.3 Order of precedence. In the event of a conflict between the text of this drawi
21、ng and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and
22、 V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design
23、, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.
24、2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4. 3.2.5 Boundry scan instruction codes. The boundry scan instruction codes shall be as specified on figure 5. 3.3 Electrical performance characteristi
25、cs and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical tes
26、t requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN
27、 number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/c
28、ompliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements
29、 of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7
30、Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. 3.8 IEEE 1149.1 compliance. These devices shall be compliant to IEEE 1149.1. Provided by IHSNot for ResaleNo re
31、production or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98578 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +115C unle
32、ss otherwise specified Group A subgroups Device type Limits Unit Min Max Low level output voltage VOL2/ DVDD= 3.14 V IOL= 12 mA 1, 2, 3 All 0.6 V High level output voltage VOH2/ DVDD= 3.14 V IOH= -12 mA 1, 2, 3 All 2.4 V Input current IIN2/ 3/ VIN= VSSto DVDD1, 2, 3 All 10 A OFF- state output leakag
33、e current IOZH,IOZL2/ VOUT= DVDDor 0 V 1, 2, 3 All 10 A Input capacitance CINf = 1 MHz at 0 V See 4.4.1b 4 All 10 15 pF Output capacitance COUTf = 1 MHz at 0 V See 4.4.1b 4 All 10 15 pF Functional tests 2/ CVDD= 1.71 V to 1.89 V DVDD= 3.14 V to 3.46 V See 4.4.1c 7, 8 All CLKIN TIMINGS Cycle time, CL
34、KIN 1 See figure 4 CLKMODE=x4 9, 10, 11 All 26.7 ns CLKMODE=x1 6.67 4/ ns Pulse duration, CLKIN high 2 CLKMODE=x4 9, 10, 11 All 9.8 ns CLKMODE=x1 2.7 ns Pulse duration, CLKIN low 3 CLKMODE=x4 9, 10, 11 All 9.8 ns CLKMODE=x1 2.7 ns Transition time, CLKIN 4 CLKMODE=x4 9, 10, 11 All 5 ns CLKMODE=x1 0.6
35、 ns CLKOUT1 TIMINGS 4/ 5/ Cycle time, CLKOUT1 1 See figure 4 CLKMODE=x4 9, 10, 11 All P 0.7 P + 0.7 ns CLKMODE=x1 P 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high 2 CLKMODE=x4 9, 10 ,11 All (P/2) - 0.5 (P/2) + 0.5 ns CLKMODE=x1 PH - 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low 3 CLKMODE=x4 9, 10, 11 All
36、 (P/2) - 0.5 (P/2) + 0.5 ns CLKMODE=x1 PL - 0.5 PL + 0.5 ns Transition time, CLKOUT1 4 CLKMODE=x4 9, 10, 11 All 0.6 ns CLKMODE=x1 0.6 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE
37、 A 5962-98578 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +115C unless otherwise specified Group A subgroups Device type Limits Unit Min Max CLKOUT2 TIMIN
38、GS 5/ Cycle time, CLKOUT2 1 See figure 4 9, 10, 11 All 2P - 0.7 2P + 0.7 ns Pulse duration, CLKOUT2 high 2 9, 10, 11 All P 0.9 P + 0.7 ns Pulse duration, CLKOUT2 low 3 9, 10, 11 All P 0.7 P + 0.9 ns Transition time, CLKOUT2 4 9, 10, 11 All 0.6 ns SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 5/ Delay time, C
39、LKOUT1 edge to SSCLK edge 1 2/ See figure 4 9, 10, 11 All (P/2) + 0.2 (P/2) + 4.2 ns Delay time, CLKOUT1 edge to SSCLK edge (1/2 clockrate) 2 2/ 9, 10, 11 All (P/2) - 1.0 (P/2) + 2.4 ns Delay time, CLKOUT1 edge to CLKOUT2 edge 3 9, 10, 11 All (P/2) - 1.0 (P/2) + 2.4 ns Delay time, CLKOUT1 edge to SD
40、CLK edge 4 2/ 9, 10, 11 All (P/2) - 1.0 (P/2) + 2.4 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98578 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHE
41、ET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +115C unless otherwise specified Group A subgroups Device type Limits Unit Min Max ASYNCHRONOUS MEMORY READ and WRITE TIMING 6/ 7/ Delay time, CLKOUT1 high to CEx valid 1 2/ See
42、figure 4 9, 10, 11 All -0.2 4.0 ns Delay time, CLKOUT1 high to BEx valid 2 2/ 9, 10, 11 All 4.0 ns Delay time, CLKOUT1 high to BEx invalid 3 9, 10, 11 All -0.2 ns Delay time, CLKOUT1 high to EAx valid 4 2/ 9, 10, 11 All 4.0 ns Delay time, CLKOUT1 high to EAx invalid 5 9, 10, 11 All -0.2 ns Setup tim
43、e, read EDx valid before CLKOUT1 high 6 2/ 9, 10, 11 All 4.0 ns Hold time, read EDx valid after CLKOUT1 high 7 2/ 9, 10, 11 All 0.8 ns Delay time, CLKOUT1 high to AOE valid 8 2/ 9, 10, 11 All -0.2 4.0 ns Delay time, CLKOUT1 high to ARE valid 9 2/ 9, 10, 11 All -0.2 4.0 ns Setup time, ARDY valid befo
44、re CLKOUT1 high 10 2/ 9, 10, 11 All 3.0 ns Hold time, ARDY valid after CLKOUT1 high 11 2/ 9, 10, 11 All 1.8 ns Delay time, CLKOUT1 high to EDx valid 12 2/ 9, 10, 11 All 4.0 ns Delay time, CLKOUT1 high to EDx invalid 13 9, 10, 11 All -0.2 ns Delay time, CLKOUT1 high to AWE valid 14 2/ 9, 10, 11 All -
45、0.2 4.0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98578 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electric
46、al performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +115C unless otherwise specified Group A subgroups Device type Limits Unit Min Max SBSRAM READ and WRITE TIMING (Full-Rate SSCLK) 8/ Output setup time, CEx valid before SSCLK high 1 2/ See figure 4 9, 10, 11 All 0.5P-1.3 n
47、s Output hold time, CEx valid after SSCLK high 2 2/ 9, 10, 11 All 0.5P-2.3 ns Output setup time, BEx valid before SSCLK high 3 2/ 9, 10, 11 All 0.5P-1.3 ns Output hold time, BEx invalid after SSCLK high 4 9, 10, 11 All 0.5P-2.3 ns Output setup time, EAx valid before SSCLK high 5 2/ 9, 10, 11 All 0.5
48、P-1.3 ns Output hold time, EAx invalid after SSCLK high 6 9, 10, 11 All 0.5P-2.3 ns Setup time, read EDx valid before SSCLK high 7 2/ 9, 10, 11 All 1.7 ns Hold time, read EDx valid after SSCLK high 8 2/ 9, 10, 11 All 1.5 ns Output setup time, SSADS valid before SSCLK high 9 2/ 9, 10, 11 All 0.5P-1.3 ns Output hold time, SSADS valid after SSCLK high 10 2/ 9, 10, 11 All 0.5P-2.3 ns Output setup time, SSOE valid before SSCLK high 11 2/ 9, 10, 11 All 0.5P-1.3 ns Output hold time, SSOE valid after SSCLK high 12 2/ 9, 10, 11 All 0.5P-2.3 ns Output setup time, ED
