1、 EIA STANDARD TP-96 Plated Through Hole Integrity Test Procedure for Electrical Connectors EIA-364-96 ANSI/EIA-364-96-2002(R2009) Approved: November 19, 2002 Reaffirmed: December 2, 2009 EIA-364-96 NOVEMBER 2002 ELECTRONIC COMPONENTS, ASSEMBLIES see figure 1. 1.4.2 Longitudinal section A section tak
2、en perpendicular to the surface of a printed circuit board; see figure 2. 1.4.3 Radial hole distortion The measurement of how far the outside edge of the plated through hole has been distorted from the original hole contour as a result of the compliant section insertion. The measurement is taken fro
3、m the transverse cross-section; see figure 1. EIA-364-96 Page 2 1.4.4 Plated through hole wall damage Any damage such as cracked plating in the plated through hole. 1.4.5 Inner conductor layer damage Includes any stretching of the inner conductor layers due to movement of the metal in the plated tho
4、ugh hole as a result of compliant section insertion. This movement of the plated through hole metal may cause the inner conductor layers to “stretch” and/or “crack”. The evaluation is taken from a longitudinal cross-section; see figure 2. 2 Test resources 2.1 Equipment 2.1.2 Low speed cutting saw or
5、 equivalent 2.1.3 Polishing equipment 2.1.4 Microscope with applicable magnification capability, (approximately between 50 and 250 times), to measure or observe the requirements as specified. 2.1.5 Photographic capability if required. 2.2 Materials Material to mount the specimens as required. Typica
6、l materials are two-part metallurgical cold mount epoxy or one of several thermosets or thermoplastics, suitable for hot mounting. Cold mounting is the preferred method. 2.3 Fixtures No fixtures are required for this method. 3 Test specimen 3.1 Description 3.1.1 The specimen consists of a compliant
7、pin inserted into a PTH. The reference document should indicate if this method is to be performed on a pin inserted once into a PTH or when a third pin is inserted into the same PTH, (usually this is performed to demonstrate repairability). If this method is used when a third pin is inserted, the pr
8、evious two pins should each be new pins. EIA-364-96 Page 3 3.1.2 The printed circuit board shall be of a given thickness, with finished and drilled hole size as specified. If not specified, the board shall be four layer equidistant throughout the thickness. The hole pattern annular rings shall be sp
9、ecified in the reference document. The two inner layers shall consist of parallel traces interconnecting all contacts in each row. The trace width shall be 0.254 millimeter (0.010 inch) and the trace thickness shall be 17 m ( ounce) copper, unless otherwise specified in the referencing document. 3.2
10、 Preparation 3.2.1 The reference document shall specify the insertion depth of the pin into the PTH. 3.2.2 The pins shall be inserted oriented as normal for their application. If not specified the measurements shall be taken after the third insertion. NOTE The printed circuit board shall be adequate
11、ly supported during the insertion process to minimize any flexure of the printed circuit board. 3.2.3 Five specimens shall be sectioned transversely and five shall be sectioned longitudinally unless otherwise specified. 3.2.4 The specimens should be placed in the metallurgical mounting material. It
12、may be possible to fit more than one specimen in the same mount. 3.2.5 The reference document shall specify where the measurements are to be performed, (e.g., at the mid-plane, near the top, or bottom sections of the printed circuit board, (unless otherwise specified in the referencing document the
13、measurement shall be taken 0.25 mm (0.010 inch) in from the insertion side of the board is recommended). 4 Test procedure 4.1 Radial hole distortion (transverse section) The allowable radial hole distortion (a) of the drilled hole contour in the PTH shall have an average distortion not greater than
14、37.5 m (0.0015 inch), with an absolute maximum distortion not greater than 50 m (0.002 inch), unless otherwise specified in the referencing document. When viewed at the maximum magnification of 75X the remaining plating (b) shall be seen to completely separate the contact from printed wiring board n
15、on conductive matrix, thus ensuring that the contact has not penetrated completely through the hole plating, see figure 1, unless otherwise specified in the referencing document. EIA-364-96 Page 4 4.2 Hole wall damage (longitudinal section) The maximum allowable distortion (c) of the connected patte
16、rn to the PTH shall be specified in the reference document. Neither the PTH nor the interconnection layer may have cracks; see figure 2. 5 Details to be specified The following details shall be specified in the referencing document: 5.1 Number of specimens, if other than 10 5.2 Printed circuit board
17、 thickness and material 5.3 Finished hole diameter, tolerance 5.4 Composition of finish in hole; e.g. copper, tin-lead, etc 5.5 Drilled hole diameter and tolerance 5.6 The PTH criteria, if other than specified in 4.1 5.7 Trace width and thickness 5.8 Annular ring dimensions 5.9 Pin insertion depth 5
18、.10 If the PTH measurements shall be performed after the first, third, or other pin insertion, and any other special requirements to perform the test 5.11 Allowable drilled hole distortion (a), if other than specified in 4.1 5.12 Type of sections required; transverse, longitudinal, or both 5.13 Allo
19、wable internal layer stretch or distortion (c); if other than specified in 4.2 5.14 Other physical damage such as cracks, pad lifting, etc. that may be cause for rejection 5.15 Depth of transverse section, if other than specified in 3.2.5 EIA-364-96 Page 5 6 Documentation Documentation shall contain
20、 the details specified in clause 5, with any exceptions, and the following: 6.1 Title of test 6.2 Description of specimen 6.3 Description of printed circuit board 6.4 Description of pin insertion method and equipment/tools, e.g., “single pin inserted with Instron or equivalent at rate of one inch pe
21、r minute“ or “25 pins inserted at once on production hydraulic press“ 6.5 If the first or third pin insertion was used. 6.6 Test equipment used, and date of last and next calibration 6.7 Values and observations 6.8 Name of operator and date of test EIA-364-96 Page 6 Figure 1 Radial hole distortion (
22、transverse section) NOTE Inner conductor layer trace shall be a minimum of 0.25 mm (0.010 inch) wide connecting to plated through hole. Figure 2 Hole wall damage (longitudinal section) Original hole contour Radial hole distortion (a) Remaining plating (b) Compliant section Cracked inner conductor la
23、yer Stretched inner conductor layer (c)Pad lifting Compliant section Annular ringInner conductor layer, see note Cracked PTH Printed wiring board EIA Document Improvement Proposal If in the review or use of this document, a potential change is made evident for safety, health or technical reasons, pl
24、ease fill in the appropriate information below and mail or FAX to: Electronic Industries Alliance Technology Strategy & Standards Department Publications Office 2500 Wilson Blvd. Arlington, VA 22201 FAX: (703) 907-7501 Document No. Document Title: Submitters Name: Telephone No.: FAX No.: e-mail: Address: Urgency of Change: Immediate: At next revision: Problem Area: a. Clause Number and/or Drawing: b. Recommended Changes: c. Reason/Rationale for Recommendation: Additional Remarks: Signature: Date: FOR EIA USE ONLY Responsible Committee: Chairman: Date comments forwarded to Committee Chairman:
