1、 ECMA-369 3rdEdition / December 2008 MAC-PHY Interface for ECMA-368 Ecma International Rue du Rhne 114 CH-1204 Geneva T/F: +41 22 849 6000/01 www.ecma-international.org IW ECMA-369.doc 02.12.2008 11:16:00 MAC-PHY Interface Specification for ECMA-368 Standard ECMA-369 3rdEdition / December 2008 . Int
2、roduction ECMA-368 specifies the PHY and MAC for a high rate ultra wideband wireless transceiver. Implementations of ECMA-368 may expose the interface between the PHY and MAC as specified herein. This Ecma Standard has been adopted by the General Assembly of December 2008. - i - Table of contents 1
3、Scope 1 2 Conformance 1 3 References 1 4 Definitions 1 5 Notational Conventions 1 6 Abbreviations and Acronyms 1 7 Overview 2 8 Interface Signal Description 2 8.1 Interface Signal Definitions 4 8.1.1 Control Interface 4 8.1.2 Data Interface 5 8.1.3 CCA Interface 5 8.1.4 Management Interface 5 8.2 PH
4、Y Operational State 6 9 Registers 6 9.1 Bit Ordering and Interpretation 6 9.2 Register Address Spaces 6 9.3 Static Parameter Definitions 7 9.4 Static Parameter Coding 12 9.5 Dynamic Register Definitions 14 9.6 Register Map 17 9.7 Register Set Access Timing 17 9.7.1 Transmit Control Registers 17 9.7.
5、2 Receive Control Registers 18 9.8 TONE-NULLING MAP CONTROL 18 10 Frame Structures 20 11 Interface Theory of Operation 25 11.1 Overview 25 11.1.1 PHY Reset Protocol 26 11.1.2 Exit from Sleep State 26 - ii - 11.1.3 Normal Operation 27 11.2 Frame Timing 27 11.3 Ranging Support 27 11.4 Transceiver Dela
6、y Definitions 28 11.5 Transceiver Turnaround Times 30 11.5.1 RX-TX Turnaround Time 30 11.5.2 TX-RX Turnaround Time 30 11.6 PREAMBLE CONTROL 30 11.6.1 Single Frame Transmission and Reception 30 11.6.2 Burst Mode Transmission 30 11.6.3 Burst Mode Reception 31 11.7 Transmit Operation 31 11.7.1 Data Bus
7、 Ownership 32 11.7.2 Single Frame Transmission Control 32 11.7.3 Burst Mode Transmission Control 34 11.7.4 Burst Mode Transmit Error Recovery 35 11.8 Receive Operation 35 11.8.1 Data Bus Ownership 35 11.8.2 Single Frame Reception Control 35 11.8.3 Burst Mode Reception Control 38 11.8.4 Burst Mode Re
8、ception Error Recovery 38 11.8.5 Zero Length Frame Reception 39 11.9 MAC Transmit Abort 39 11.10 MAC Receive Abort 40 11.11 Error Conditions 40 11.11.1 Transmit Error Conditions 40 11.11.2 Receive Error Conditions 40 11.12 Clear Channel Assessment 42 11.12.1 CCA Interface Signals 43 11.12.2 Operatio
9、n of the CCA Interface 43 11.13 Management Interface 44 11.13.1 Management Interface Signals 44 11.13.2 Operation of the Management Interface 44 11.13.3 Examples 46 Annex A (informative) Electrical Specifications 47 Annex B (informative) PHY Vendor and Version Coding 51 - 1 - 1 Scope This Ecma Stand
10、ard specifies the interface between implementations of the PHY and MAC as specified in ECMA-368. 2 Conformance PHY and MAC implementations of ECMA-368 conform to this Standard by implementing the interface specified herein. 3 References ECMA-368 High Rate Ultra Wideband PHY and MAC Standard 4 Defini
11、tions For the purposes of this document, the definitions given in ECMA-368 apply. 5 Notational Conventions The use of the word shall is meant to indicate a requirement which is mandated by the Standard, i.e. it is required to implement that particular feature with no deviation in order to conform to
12、 the Standard. The use of the word should is meant to recommend one particular course of action over several other possibilities, however without mentioning or excluding these others. The use of the word may is meant to indicate that a particular course of action is permitted. The use of the word ca
13、n is synonymous with is able to it is meant to indicate a capability or a possibility. All floating-point values have been rounded to 4 decimal places. An exclamation mark preceding a signal indicates that the signal is active low. 6 Abbreviations and Acronyms BM Burst Mode CCA Clear Channel Assessm
14、ent CRC Cyclic Redundancy Code FCS Frame Check Sequence FFI Fixed-Frequency Interleaving HCS Header Check Sequence LQI Link Quality Indicator lsb Least-Significant Bit MAC Medium Access Control MIFS Minimum Interframe Space msb Most-Significant Bit PHY Physical (layer) PLCP Physical Layer Convergenc
15、e Protocol PT Preamble Type - 2 - RSSI Received Signal Strength Indicator RX Receive or Receiver SIFS Short Interframe Space TF Time-Frequency TFC Time-Frequency Code TFI Time-Frequency Interleaving TX Transmit or Transmitter 7 Overview Clause 8 defines the interface signals, their directions and fu
16、nctions. Clause 9 defines the interface parameters and registers. A recommended mapping for PHY parameters is provided along with the register map for PHY registers and setup and hold timing for register access. Clause 10 defines the frame formats for data exchanges over the interface. Clause 11 is
17、the Theory of Operation for the complete interface covering the PHY states and transitions, reset and sleep protocols, frame timing references, preamble control and transmit and receive operations for both single frame and burst mode operation as well as receive error cases. The section is completed
18、 by definition of the CCA and Management interface protocols. There are two annexes to this specification. Annex A provides an Electrical Interface and Annex B defines formats for two managed identifiers. 8 Interface Signal Description The MAC-PHY signal interface is depicted in Figure 1. It consist
19、s of the Data Interface including an 8-bit data bus, the Control Interface, the CCA Interface and the Management Interface. The Data Interface, which is used to transfer data to and from the MAC, operates differently depending on the state of the PHY. The Control Interface is used by the MAC to cont
20、rol the operating state of the PHY and by the PHY to indicate TX/RX status to the MAC. The CCA Interface is used for Clear Channel Assessment status indication. The Management Interface is used to access the PHY registers. - 3 - PHY MACCCA_STATUSCCA InterfaceSERIAL_DATAManagement InterfacePCLKDATA_E
21、NDATA7:0Data InterfaceTX_ENRX_ENPHY_ACTIVEPHY_RESETSTOPCControl InterfaceFigure 1 PHY-MAC interface signals Table 1, Table 2, Table 3 and Table 4 define the signals in the Control Interface, Data Interface, CCA Interface and Management Interface, respectively. The operational mode of the Data Interf
22、ace in each PHY state is summarized in Table 5. - 4 - 8.1 Interface Signal Definitions 8.1.1 Control Interface Table 1 Control Interface Signals SIGNAL Width (Bits) DIR DESCRIPTION !PHY_RESET 1 MAC to PHY !PHY_RESET is asserted for PHY specific interval PHYResetTime to clear all PHY variables and re
23、set the PHY to its initial state. The PHY writes STANDBY to PMMODE and transitions to STANDBY state after !PHY_RESET is de-asserted and reset operations have completed. !PHY_RESET is asynchronous to PCLK. !PHY_RESET is ACTIVE LOW. TX_EN 1 MAC to PHY TX_EN is used to place the PHY in TRANSMIT State.
24、Its secondary use (with RX_EN) is to transition from SLEEP to STANDBY when the PHY clock source has been stopped for power saving. TX_EN is synchronous to PCLK except in SLEEP state. TX_EN is ACTIVE HIGH. RX_EN 1 MAC to PHY RX_EN is used to place the PHY in RECEIVE State. Its secondary use (with TX_
25、EN) is to transition from SLEEP to STANDBY when the PHY clock source has been stopped for power saving. RX_EN is synchronous to PCLK except in SLEEP state. RX_EN is ACTIVE HIGH. PHY_ACTIVE 1 PHY to MAC PHY_ACTIVE is used by the PHY to indicate that it is either transmitting or receiving a frame over
26、 the air. In TRANSMIT state, the rising edge of PHY_ACTIVE indicates the start of frame at the local antenna and the falling edge indicates that the entire frame has been transmitted over the air. In RECEIVE state, the rising edge of this signal indicates that the start of the preamble has been dete
27、cted (SyncDelay + the preceding synchronization fields earlier) and the falling edge indicates that the entire frame has been received (PHYActiveDelay earlier) at the local antenna. PHY_ACTIVE is also used in the special cases of Exit from SLEEP and RESET. PHY_ACTIVE is synchronous to PCLK. PHY_ACTI
28、VE is ACTIVE HIGH. STOPC (optional) 1 MAC to PHY On/Off signal for PCLK in STANDBY state. PCLK is active when STOPC is de-asserted and not active when STOPC is asserted. STOPC is asynchronous to PCLK. STOPC is ACTIVE HIGH. - 5 - 8.1.2 Data Interface Table 2 Data Interface Signals SIGNAL Width (Bits)
29、 DIR DESCRIPTION PCLK 1 PHY to MAC Interface clock provided by the PHY. Interface signals are synchronous to the rising edge of PCLK (see Annex A). The nominal rate of PCLK is 66MHz. DATA_EN 1 PHY to MAC In TRANSMIT state, this signal is used by the PHY to request more data from the MAC. In RECEIVE
30、state, it is used to indicate to the MAC that there is valid data on the DATA7:0 bus. DATA_EN is synchronous to PCLK. DATA_EN is ACTIVE HIGH. DATA7:0 8 Bi-directional DATA7:0 is an 8-bit wide data bus driven by the MAC in TRANSMIT state and by the PHY in all other states including SLEEP. DATA7:0 is
31、synchronous to PCLK whether driven by the PHY or the MAC. DATA7:0 ONE is HIGH. 8.1.3 CCA Interface Table 3 CCA Interface Signals SIGNAL Width (Bits) DIR DESCRIPTION CCA_STATUS 1 PHY to MAC The PHY returns CCA_STATUS after a CCA request is initiated by the MAC writing to the CCRE register via SERIAL_
32、DATA. CCA_STATUS is synchronous to PCLK. CCA_STATUS is ACTIVE HIGH. 8.1.4 Management Interface Table 4 Management Interface Signals SIGNAL Width (Bits) DIR DESCRIPTION SERIAL_DATA 1 Bi-directional The MAC writes control and address bits to SERIAL_DATA to initiate register access. SERIAL_DATA is driv
33、en by the MAC for Write operations. It is driven by the MAC for control and address parts of Read operations and by the PHY for the data part of Read operations. SERIAL_DATA is synchronous to PCLK. SERIAL_DATA ONE is HIGH. - 6 - 8.2 PHY Operational State Table 5 PHY Readiness State STATE DESCRIPTION
34、 RESET Transitional state in which the configuration parameters are reset to default values. RESET is asynchronous to PCLK (see 11.1.1). SLEEP The radio is off. PCLK is off (see 11.1.2). STANDBY The radio is off. PCLK is on (unless STOPC is asserted). STANDBY is a higher activity state than SLEE. RE
35、ADY Parts of the radio are on. PCLK is on. TRANSMIT The PHY Tx paths and the radio transmit path are active. PCLK is on. RECEIVE The PHY Rx paths and the radio receive path are active. PCLK is on. 9 Registers In registers, bit positions that are defined as reserved shall be ignored on reading and se
36、t to ZERO on writing. Two sets of parameters are defined to allow the MAC to control the operation of the PHY and permit information to be provided by the PHY to the MAC. STATIC Parameters These parameters are fixed for a given instantiation of the MAC and PHY. They can be considered to be constants
37、 for the purposes of the definition of the MAC-PHY Interface and their values can be defined in a given PHY data sheet, stored as constants in the system implementation or provided by any other means. The static parameters are defined in Table 6. DYNAMIC Parameters These parameters may be changed du
38、ring operation of the system, and affect operation of the PHY. They shall be implemented within the PHY as registers and can be read and/or written (depending on the specific parameter) via the Serial Management Interface. The dynamic registers are defined in Table 7. 9.1 Bit Ordering and Interpreta
39、tion All data structures, except where explicitly stated, are defined with the bit order as defined in Figure 4. Reserved bits shall be ignored on reading and set to ZERO on writing. 9.2 Register Address Spaces The PHY interface shall have 256 addressable 8-bit registers (8-bit address, 8-bit data)
40、divided into 3 regions: Dynamic Register region defined by this specification: address 00(h)1F(h) Optional Static Parameter region defined by this specification: address 20(h)7F(h) Vendor Specific Register region for vender defined registers: address 80(h)FF(h) - 7 - 9.3 Static Parameter Definitions
41、 Table 6 Description of Static Parameters REGISTER OCTETS DEFINITION SupportedRegDomains 2 Supported regulatory regions. Bit set to ONE if supported, ZERO otherwiseFirst Octet Bit Domain 2:0 Reserved 3 European Telecommunications Standards Institute (ETSI) 4 Federal Communications Commission (FCC) 5
42、 Industry Canada (IC) 6 Association of Radio Industries and Businesses (ARIB) 7 Ministry of Information and Communications (MIC) Second Octet Bit Domain 7:0 Reserved SupportedDataRates 2 Set of supported data rates. Bit set to ONE if supported, ZERO otherwise Bit Data Rate Supported 0 53,33 Mbps 1 R
43、ESERVED 2 80 Mbps 3 106,7 Mbps 4 RESERVED 5 160 Mbps 6 200 Mbps 7 320 Mbps 8 400 Mbps 9 480 Mbps 15:10 RESERVED NumChannelsSupported 1 Number of supported channels - 8 - Table 6 Description of Static Parameters (continued) REGISTER OCTETS DEFINITION SupportedDiversity 1 Number of additional antennas
44、 provided for diversity 1:0 Number of additional receive antennas 3:2 Reserved 5:4 Number of additional transmit antennas 7:6 Reserved SupportedChannels 1 Supported Channels. Bit set to ONE if supported, ZERO otherwise Bit Channel Supported 0 TFC channels in band group 1 supported 1 TFC channels in
45、band group 2 supported 2 TFC channels in band group 3 supported 3 TFC channels in band group 4 supported 4 TFC channels in band group 5 supported 5 TFC channels in band group 6 supported 7:6 RESERVED TXPowerLevel 16 Array of transmit power levels. Each element from 0 to (NumTxPowerLevels-1) of the a
46、rray holds a supported transmit power. The format of the power level datum is PHY vendor specific. The other elements shall be set to zero. Element 0 shall hold the maximum transmit power supported. NumTxPowerLevels 1 Number of transmit power levels supported. Permitted range (015) with 0 meaning a
47、single fixed power level only. 3:0 number of levels (permitted range 015) 7:4 RESERVED SupportedPHYStates 1 Supported PHY States. Bit set to ONE if supported, ZERO otherwise. 0 SLEEP 1 STANDBY 2 READY 3 TRANSMIT 4 RECEIVE 7:5 RESERVED PHYClockAccuracy 1 Accuracy of PHY clock in parts per million. PH
48、YResetTime 1 Interval during which !PHY_RESET shall be held asserted for the PHY to perform the RESET operation. Units us. - 9 - Table 6 Description of Static Parameters (continued) REGISTER OCTETS DEFINITION WakeUpDelay 2 Time to transition from SLEEP mode to STANDBY mode. Units 0,5 s. TurnOnDelay
49、2 Radio turn-on time during transition from STANDBY mode to READY mode. Units 0,5 s. TxDataDelay 1 Delay, not greater than 4 s, before the end of the preamble at the local antenna before which the PHY will not assert DATA_EN to request the first octet of header data. (See 11.4)Units s. RxDataDelay 2 Maximum delay from the end of the received PLCP header at the local antenna to the transfer of the last octet of the PLCP header and HeaderError octet across the MAC-PHY i
