1、ANSI/ElA-469-0-2006 Approved: April 6,2006 EIA STANDARD STANDARD TEST METHOD FOR DESTRUCTIVE PHYSICAL ANALYSIS (DPA) OF CERAMIC MONOLITHIC CAPACITORS EIA/E CA-469-D (Revision of EIA-469-C) APRIL 2006 Electronic Cornpanen it may include many finishing lots, depending on the control document. Interban
2、d dimension: The distance between opposite end metallization bands on a capacitor element. Interface: The junction of two layers in a layered device, for example, the junction of electrode to dielectric layers or between two ceramic sheet layers. Intermetallic: A solution of two metallic elements fo
3、rmed during reflow or due to certain other conditions involving temperature and time, for example, the copper/tin intermetallic formed between a copper surface and a tin/lead solder when the solder is reflowed against the copper surface. Knitline: Generally, the bonding interface between two layers
4、of bondable materials; these may be the same, similar, or different materials. Specifically, in ceramic multilayer capacitors, the interface of bonding between two ceramic sheets or a ceramic and metallic interface. Knitline delamination: Specifically, a delamination that occurs in one of the knitli
5、nes of an end margin, in the same plane as an opposed electrode. Leaching: The erosion of end metal from a chip capacitor due to the action of molten solder, wherein the end metal is dissolved and put into solution with the solder. Length: The dimension running from termination to termination. In so
6、me chip capacitor designs, the length may be less than the width of the element. Lot: The general designation of a quantity of product which is of the same raw material origin, design and lot date code, and was manufactured as a uniquely designated group through the same processes. This could be a c
7、hip lot, a finishing lot, or an inspection lot. Lot date code: A designation used for lot identification that is made up of following sequence: 1) a 2-digit year code; 2) a 2-digit week code; 3) an alpha or alphanumeric code that is unique for one lot manufactured during a given year and week, e.g.,
8、 9305ZX, 931 5A7, 91 51 L, etc. This identifier must be printed on each part or each package, and on all pertinent data, photographs, samples, etc. Margin: The ceramic portion of a chip element which envelopes the active area. Metallization band: The portion of the end metallization which extends al
9、ong the exterior of the chip from the end of the chip element toward its longitudinal center for distances varying generally from 0.25 mm to 1 .O2 mm (0.01 in to 0.04 in). Microcrack: A very fine narrow crack in the ceramic that is visible only at relatively high magnifications (generally above 150X
10、) with the aid of indirect or dark field or polarized lighting. True Microcrack occur due to internal chip element stresses or relief of such stresses. Mounting: The process, during DPA, consisting of setting the sample specimens up on an adhesive surface and surrounding them with a retainer ring, r
11、eady for pouring of the potting medium. Opposed electrodes: See 3.28, Electrically opposed electrodes. Overlap view: The longitudinal sectional view of monolithic capacitors, hybrids or leaded, showing the overlapped electrode edges, end margins, end metallizations, and chip to lead solder joint, th
12、e plane being perpendicular to the electrodes and ceramic layers (see figure C.1.). EIA-469-D Page 7 Pinhole: By definition, an open cavity in the ceramic cover plate, generally circular in shape, which is no larger than 0.05 mm (0.002 in) in diameter and has appreciable depth. Potting: See 3.1 O, C
13、asting. Potting medium: See 3.1 1, Casting material. Pull-out: The undesirable shattering, crumbling, and removal of materials from the specimen surface during abrasive sectioning or polishing. this is a problem particularly around voids, delaminations or other unsupported edges. Random sample: A gr
14、oup of specimens drawn from a population of similar specimens (a lot) without regard for any selection principle or plan, where each individual has an equal chance of being chosen or passed over. Sample: A group of specimens drawn from a much larger group of similar specimens for the purpose of gath
15、ering information pertinent to the large group (population). Sample specimen: See 3.63, Sample unit. Sample unit: One member of a sample such as a capacitor. A sample of 20 pieces has 20 sample units. Scavenging: The action of molten solder upon chip capacitor end metal, by which the solder dissolve
16、s and takes all or part of the end metal into solution. Side margin: The portion of the ceramic envelope which is parallel to the thickness by length plane and which extends from the side of the electrodes to the outside edge of the chip element. Also see 3.50, Margin. Side margin view: The transver
17、se sectional view of a sectioned sample unit, showing the side margins, cover plates and electrode edges. This is perpendicular to the overlap view and the electrode plane (see figure C.2.). Solder fill: The bulk of solder metal which occupies the space between a capacitor lead wire and the capacito
18、r element, which constitutes the solder joint between lead and capacitor element. Solder fillet: The externally visible portion of the solder metal which attaches the lead wire to the capacitor element and is characterized by a smooth and tapering convergence of solder metal with lead wire and capac
19、itor element, the surface of the solder often being somewhat concave. Solder wetting: The condition whereby molten solder metal and a heated base metal surface fuse, forming an atomic interface (usually in the presence of a flux such as rosin). The liquid solder forms a dihedral angle with the base
20、metal surface, generally less than 75“, for adequate solder-to-base metal bonding and with the anchorage area between base metal and solder ideally being 100%. Stress relief cracking: Cracks generally seen in the overlap view, but also in the side margin view, associated usually with the cover plate
21、s and the outer two or three electrodes. These are artifacts of the sectioning process due to grinding samples without decapsulation before mounting or due to inadequate edge support. They are not defects and must not be assessed as such. Striations: Longitudinal grooves in the side margin ceramic s
22、urface at the layer interfaces, where layer-to- layer adhesion was disturbed during laminator chip ejection, chip dicing from a multichip pad, or chip handling before chip firing. These are distinguishable from delaminations in that the bottom of striations are visibly firing bonded, while the botto
23、ms of delaminations or cracks cannot be visually determined. Subsample: A part of a total sample distinguishable from the remainder of the sample by a consideration such as the orientation of the view or plane of inspection, or by some separate requirement such as solderability testing which does no
24、t pertain to the other DPA sample units. EIA-469-D Page 8 Surface fracturing: Shallow, oblique cracking of ceramic between electrodes and in cover plates due to grinding stresses or chatter of the potted sample on the moving surface of the abrasive grit where the sample may alternately grab and slid
25、e. This artifact may be induced also during hand polishing operations. Surface relief: The difference in the level or height of the ground or polished specimens between the relatively hard and softer materials. The metal portions erode faster during grinding and polishing than do the harder ceramic
26、surfaces. Hand polishing produces considerable surface relief. Termination metallization: See 3.33. End metallization. Terminating electrode end: The end of an electrode which makes contact with the end metallization. Thermal shock crack: A ceramic crack due to sudden thermal change or unequal condu
27、ction of heat through the ceramic chip element. Thickness: The dimension of a chip element that is perpendicular to length, width, and the electrode planes. Void: An empty space in the ceramic, or end metallization, or lead-to-chip solder, or encapsulation. Wetting: See 3.69, Solder weffing. Width:
28、The chip dimension perpendicular to the length and parallel to the electrode planes. 4 Recommended procedures and methods The following procedures and methods are essential for DPA performed on ceramic capacitors. These are presented in logical, sequential order. Where more than one method for an ac
29、tivity is acceptable, the preferred method is indicated. 4.1 Visual appearance of DPA sample units Since the primary purposes of DPA is determination of internal physical quality, specimens that are unacceptable according to external visual criteria should not be used for DPA. If such units are incl
30、uded in the DPA, then appropriate records of the type and number of external defects must be kept to avoid confusing the internal examination performed during DPA. External visual inspection of decapsulated, leaded capacitors shall include both chip element and end terminations, including lead attac
31、hment. However, if a lead or leads on a decapsulated capacitor appear(s) loose or dislodged, a supplementary sample of five specimens shall be used to determine lead attachment integrity. These five capacitors shall be potted as manufactured, without decapsulation, and only the lead attachment crite
32、ria in 4.1.2 shall apply. The chip element shall not be examined because stress relief cracks are likely to occur in these and such features are artifacts of grinding or polishing. They are not defects and shall not be counted as such. The preparation of the supplementary sample is described in 4.2.
33、 4.1 .I Decapsulated capacitor external visual defect criteria a) Any capacitor chip element that fails the procurement specifications external visual criteria. b) leaded devices or less than 90% solder joint between nailheads and end metallization for axially leaded devices. See annex A.1. Lead-to-
34、chip solder coverage exhibiting less than 80% filleting between lead and chip for radially NOTE-Missing or dislodged lead (not a defect). See 4.1 on supplementary sample. EIA-469-D Page 9 4.1.2 These criteria are for the purpose of judging lead-to-chip element attachment integrity and in that sense
35、or to that extent form a part of the DPA inspection when applicable. If any of the five specimens in a Supplementary sample fails the criteria of 4.1.2, it shall be cause for rejecting the lot. Individual defectives per these criteria in this supplementary sample may not be applied to the normal DPA
36、 sample acceptance criteria (AQL). However, as noted in 5.1 .lob, 4.1.2 and 4.1.2d are made a part of 5.1 .IO for evaluation Of lead attachment of the regular DPA sample units. In case of a dispute between the results of the supplementary sample and the DPA sample with regard to lead attachment inte
37、grity, the results from the supplementary sample shall prevail. Supplementary sample criteria (for sectioned and polished sample) This inspection shall be performed using 30X to 60X magnification. See illustrations in annex B. Criteria follow: a) Cracked solder joint between lead and capacitor eleme
38、nt or nonwetting of the capacitor end metallization or the lead. b) Crack(s) in the solder joint, as indicated by the intrusion of encapsulation material into the crack(s). NOTE-A small round bottomed declivity or concavity between lead and chip element where full solder wetting is obvious may conta
39、in encapsulant without failing this criterion (see annex B). c) Solder voids, their major dimensions cumulatively measured, larger than one-half the thickness of the chip element, regardless of solder fill. d) Three or more solder voids in a sectional view of a single solder joint, where each is lar
40、ger than 0.200 mm (0.008 in), regardless of cumulative measurement related to chip thickness. 4.2 Sample preparation methods 4.2.1 Introduction This Standard requires that encapsulated (molded) capacitors be decapsulated before mounting and casting for sectioning. This must be done to avoid inducing
41、 artificial damage to the chip element due to unequal compression relief in the molded parts during abrasive sectioning (see 3.70, Stress relief cracks). Damage similar to stress relief cracking also can be caused by inadequate support of the sample units if the potting medium does not harden suffic
42、iently during curing. Decapsulation materials and procedures must be such that minimum damage is done to the chip element, leads, and lead-to-chip attachment. The correct decapsulant to use will vary somewhat depending on the type of encapsulation material to be removed. NOTE-All chemicals used for
43、decapsulation will attack material interfaces and surfaces to some extent. For the types of decapsulants recommended in this Standard, some mechanical force is required for removing the encapsulation material, while endeavoring to preserve the lead attachment integrity. 4.2.2 Decapsulation Decapsula
44、tion is, of course, the removal of the encapsulation from the leaded capacitor element. The following materials are recommended for removal of the more usual glass-filled epoxy encapsulants from finished capacitors: Technical name Common name Dimethylformamide DMF N-Methyl-2-Pyrrolidone M-Pyrol EIA-
45、469-D Page 10 NOTE-All decapsulants present hazards to the users. Strict adherence to the manufacturers safety instructions and recommendations and good laboratory practices are mandatory. The two materials recommended above are highly polar Organic Solvents. Both are flammable, but not explosive un
46、der recornmended conditions of usage. Both must be used under an adequately ventilated fume hood. DMF should not be heated to more than 170 “C. M-Pyrol should be kept below 220 “C. These temperatures will allow the recornmended procedures to be safely performed. Disposal of these materials must be i
47、n accordance with OSHA regulations. Safety and hazard information is available from the manufacturers. The manufacturer of DMF is DuPont; the maker of M-Pyrol is GAF If the product being decapsulated does not respond to the solvents recommended in this specification, the manufacturer of that product
48、 should be contacted for information on its decapsulation, regarding both chemical and procedure issues. When the above recommended decapsulants are used, the following is a correct procedure: 4.2.2.1 Decapsulation procedure a) Cut leads off to a length of approximately 1 .O mm (0.04 in). b) Place t
49、he devices to be decapsulated into a borosilicate glass (e.g., PyrexTM) beaker and cover them with approximately 13 mm (0.5 in) of the decapsulant (DMF or M-Pyrol). Cover the beaker with an appropriate watch glass. A refluxing flask system may be used to control and condense vapors. c) Set the beaker on a controlled heat source capable of 250 OC, cover and allow to reach the boiling point and adjust the heat to maintain a slow boiling action for a period of 30 min to 90 min, depending on the size and configuration of the encapsulated capacitor. DMF boils at slightly over 150 OC, while M-Pyr
