1、BRITISH STANDARD BS EN 61188-5-6:2003 Printed boards and printed board assemblies Design and use Part 5-6: Attachment (land/joint) considerations Chip carriers with J-leads on four sides The European Standard EN 61188-5-6:2003 has the status of a British Standard ICS 31.190 BS EN 61188-5-6:2003 This
2、 British Standard was published under the authority of the Standards Policy and Strategy Committee on 26 June 2003 BSI 26 June 2003 ISBN 0 580 42110 4 National foreword This British Standard is the official English language version of EN 61188-5-6:2003. It is identical with IEC 61188-5-6:2003. The U
3、K participation in its preparation was entrusted to Technical Committee EPL/501, Electronic assembly technology, which has the responsibility to: A list of organizations represented on this committee can be obtained on request to its secretary. Cross-references The British Standards which implement
4、international or European publications referred to in this document may be found in the BSI Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Search” facility of the BSI Electronic Catalogue or of British Standards Online. This publication does not
5、 purport to include all the necessary provisions of a contract. Users are responsible for its correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. aid enquirers to understand the text; present to the responsible international/European com
6、mittee any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. Summary of pages This document comprises a front cover, an inside front cover, the EN title page, pages 2 to
7、 19 and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. Amendments issued since publication Amd. No. Date CommentsEUROPEAN STANDARD EN 61188-5-6 NORME EUROPENNE EUROPISCHE NORM April 2003 CENELEC European Committee for Electrotechnical Sta
8、ndardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2003 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 61188-5-
9、6:2003 E ICS 31.190 English version Printed boards and printed board assemblies Design and use Part 5-6: Attachment (land/joint) considerations Chip carriers with J-leads on four sides (IEC 61188-5-6:2003) Cartes imprimes et cartes imprimes quipes Conception et utilisation Partie 5-6: Considrations
10、sur les liaisons pistes-soudures Composants sorties en J sur quatre cts (CEI 61188-5-6:2003) Leiterplatten und Flachbaugruppen - Konstruktion und Anwendung Teil 5-6: Betrachtungen zur Montage (Anschlussflche/Verbindung) - Bauelemente mit J-frmigen Anschlssen auf vier Seiten (IEC 61188-5-6:2003) This
11、 European Standard was approved by CENELEC on 2003-03-01. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical refe
12、rences concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC
13、member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Luxembourg
14、, Malta, Netherlands, Norway, Portugal, Slovakia, Spain, Sweden, Switzerland and United Kingdom. EN 68118-5-6:0230 - - 2 Foreword The text of document 91/338/FDIS, future edition 1 of IEC 61188-5-6, prepared by IEC TC 91, Electronics assembly technology, was submitted to the IEC-CENELEC parallel vot
15、e and was approved by CENELEC as EN 61188-5-6 on 2003-03-01. This European Standard should be read in conjunction with EN 61188-5-1:2002. The following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorse
16、ment (dop) 2003-12-01 latest date by which the national standards conflicting with the EN have to be withdrawn (dow) 2006-03-01 Annexes designated “normative“ are part of the body of the standard. In this standard, annex ZA is normative. Annex ZA has been added by CENELEC. _ Endorsement notice The t
17、ext of the International Standard IEC 61188-5-6:2003 was approved by CENELEC as a European Standard without any modification. _ Page2 EN6118856:2003CONTENTS INTRODUCTION.4 1 Scope and object5 2 Normative references.5 3 General information6 3.1 General component description.6 3.2 Marking.6 3.3 Carrie
18、r packaging format.6 3.4 Process considerations .6 4 QFJ (square)6 4.1 Introductory remark.6 4.2 Component description6 4.3 Component dimensions.8 4.4 Solder joint fillet design .8 4.5 Land pattern dimensions .10 5 QFJ (rectangular).12 5.1 Introductory remark.12 5.2 Component description12 5.3 Compo
19、nent dimensions.13 5.4 Solder joint fillet design .14 5.5 Land pattern dimensions .16 Annex ZA (normative) Normative references to international publications with their corresponding European publications .18 Bibliography19 Figure 1 QFJ (square)7 Figure 2 QFJ (square) dimensions .8 Figure 3 Solder j
20、oint fillet design of QFJ square component with different levels (see IEC 61188-5-1, Table 5)10 Figure 4 QFJ (square) land pattern dimensions12 Figure 5 QFJ (rectangular).12 Figure 6 QFJ (rectangular) dimensions 14 Figure 7 Solder joint fillet design of QFJ rectangular component with different level
21、s (see IEC 61188-5-1, Table 5)16 Figure 8 QFJ (rectangular) land pattern dimensions.17 Page3 EN6118856:2003 INTRODUCTION This part of IEC 61188 covers land patterns for components with J leads on four sides. Each clause contains information in accordance with the following format: The proposed land
22、pattern dimensions in this standard are based upon the fundamental tolerance calculation combined with the given land protrusions and courtyard excesses (see IEC 61188-5-1). The courtyard covers all issues pertaining to normal manufacturing needs. The land pattern dimensions covered in this standard
23、 are generally applicable for reflowed solder paste processes. For immersion soldering processes (e.g. wave, jet, drag soldering), lands may have to be modified to prevent shadowing and shorting (e.g. by extending land length parallel to the direction of motion of the board and/or provision of solde
24、r thieves). This specification offers a threefold land pattern dimensioning (levels 1, 2, and 3) on the basis of a threefold set of land protrusions and courtyard excesses maximum (max.), median (mdn.), and minimum (min.). Each land pattern has been assigned an identification number to indicate the
25、characteristics of the specific robustness of the land patterns. Users also have the opportunity to organize the information to suit their particular design. This standard assumes that land dimensions are always larger than component termination or lead outlines. If a user has good reason to use sol
26、der resist to limit wetting on a land, or to use lands smaller than component terminations, or to apply a concept different from that of IEC 61188-5-1, this standard may not apply. It is the responsibility of the user to verify the surface mounting devices (SMD) land patterns used for achieving an u
27、ndisturbed mounting process, including testing, and an ensured reliability for the product stress conditions when in use. Dimensions of the components listed in this standard are those available on the market, and are for reference purposes only. Page4 EN6118856:2003PRINTED BOARDS AND PRINTED BOARD
28、ASSEMBLIES DESIGN AND USE Part 5-6: Attachment (land/joint) considerations Chip carriers with J-leads on four sides 1 Scope and object This part of IEC 61188 provides information on land pattern geometries used for the surface attachment of electronic components with J leads on four sides. The objec
29、t of this standard is to provide the appropriate size, shape and tolerances of surface mount land patterns so as to ensure sufficient area for the appropriate solder fillet, and also allow for inspection, testing and reworking of resulting solder joints. Each clause contains a specific set of criter
30、ia, setting out details on the component, the component dimensions, the solder joint design and the land pattern dimensions. NOTE The acronym QFJ is the naming convention used by Japan; the acronym PLCC is the naming convention used by the USA for these components. 2 Normative references The followi
31、ng referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 60068-2-58, Environmental testing Part 2-58: Tests Test
32、Td: Test methods for solderability, resistance to dissolution of metallization and soldering heat of surface mounting devices (SMD) IEC 60191-2, Mechanical standardisation of semiconductor devices Part 2: Dimensions IEC 61188-5-1, Printed boards and printed board assemblies Design and use Part 5-1:
33、Attachment (land/joint) considerations Generic requirements IEC 61760-1, Surface mounting technology Part 1: Standard method for the specification of surface mounting components (SMDs) Page5 EN6118856:20033 General information 3.1 General component description The component consists of quad flat J-l
34、ead packages with terminations, which extend beyond the package outlines. The shape of the packages can be either square or rectangular. These terminations typically separate the body of the package from the packaging and interconnect structure (P&IS) for reasons of clearing, inspecting or accommoda
35、ting differences in thermal expansion. In plastic leaded chip carriers, the primary packaging distinction concerns the point at which a chip is incorporated into the package. A pre-molded package is supplied as a leaded body with an open cavity for chip attachment. A post-molded body part typically
36、has the chip attached to a lead frame with an insulating plastic body molded around the assembly. 3.2 Marking The QFJ (square and rectangular) families of parts are generally marked with the manufacturers part numbers, name or symbol, and a pin 1 indicator. Some parts may have a pin 1 feature in the
37、 case shape instead of a pin 1 marking. Additional markings may include date-code manufacturing lot and/or manufacturing location. 3.3 Carrier packaging format The carrier packaging format may be provided in tubes but embossed carrier taping is preferred for best handling and high volume application
38、s. Bulk packaging is not acceptable because of lead coplanarity required for placement and soldering. 3.4 Process considerations QFJ packages are normally processed by reflow solder operations (see IEC 60068-2-58). High lead-count fine pitch parts may require special processing outside the normal pi
39、ck/place and reflow manufacturing operations. 4 QFJ (square) 4.1 Introductory remark This clause provides the component and land pattern dimensions for square QFJ (quad flat J- lead) components. Basic construction is also covered. Figures 2 and 3 provide a listing of the tolerances and target solder
40、 joint dimensions used to arrive at the land pattern dimensions. 4.2 Component description QFJs are widely used in variety of applications for commercial, industrial or military electronics. 4.2.1 Basic construction See Figure 1. Page6 EN6118856:2003IEC 3270/02Figure 1 QFJ (square) QFJs (quad flat J
41、-lead packages) are employed where a hermetic seal is not required. Other constraints include a limited temperature range (typically 0 C or 70 C) and nominal environmental protection. QFJs have the advantage of low cost as compared to ceramic packages. 4.2.2 Termination materials High lead-end copla
42、narity in surface mounted lead chip carriers is an important factor in reliable solder attachment to the printed board. Planarity may be measured from the lowest three leads of a leaded package. Coplanarity of 0,1 mm maximum is recommended with a preference for 0,05 mm. The pre-molded plastic chip c
43、arrier was designed to be connected to the packaging and interconnection (P&l) substrate by means of a socket. Spring pressure on both sides of the package is intended to constrain movement as well as allow for substrate warpage as high as 0,5 %. Solder attach to the P&l substrate is also possible.
44、The design is also intended to make use of silicone encapsulate technology for chip coverage and protection. The pre- and post-molded plastic leaded chip carrier is composed of a composite metal/dielectric assembly that includes a conductor lead frame and a molded insulating body. In both types of p
45、lastic chip carriers, all necessary plating operations are performed by the package manufacturer to eliminate tinning or plating by the user. 4.2.3 Marking All parts shall be marked with a part number and “Pin 1” location. The “Pin 1” location may be molded into the plastic body or marked with ink.
46、4.2.4 Carrier package format The carrier package format for flat packs may be provided in tubes but, in most instances, flat packs are delivered in embossed taping. 4.2.5 Process considerations Parts should be capable of withstanding ten cycles through a standard reflow system operating at 235 C. Ea
47、ch cycle shall consist of a 60 s exposure at 235 C. Parts must also be capable of withstanding a minimum of 10 s immersion in molten solder at 260 C. The components shall meet the requirements of IEC 61760-1. Page7 EN6118856:20034.3 Component dimensions Figures 2 to 4 provide the component dimension
48、s for QFJ (square) components. H W S J L T A P B L IEC 3271/02Dimensions in millimetres L W T A B J H P Component identifier Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Ref Max. Basic QFJ-20 9,60 10,21 0,33 0,58 1,20 1,74 8,71 9,22 8,71 9,22 7,87 4,57 1,27 QFJ-28 12,14 12,75 0,33 0,58 1,20 1,7
49、4 11,25 11,76 11,25 11,76 10,41 4,57 1,27 QFJ-44 17,22 17,83 0,33 0,58 1,20 1,74 16,33 16,84 16,33 16,84 15,49 4,57 1,27 QFJ-52 19,76 20,37 0,33 0,58 1,20 1,74 18,87 19,38 18,87 19,38 18,03 5,08 1,27 QFJ-68 24,84 25,45 0,33 0,58 1,20 1,74 23,95 24,51 23,95 24,51 23,11 5,08 1,27 QFJ-84 29,92 30,53 0,33 0,58 1,20 1,74 29,03 29,59 29,03 29,59 28,19 5,08 1,27 QFJ-100 35,00 35,61 0,33 0,58 1,20 1,74
