1、BRITISH STANDARD Delay and power calculation standards Part 1 : Integrated circuit delay and power calculation systems The European Standard EN 61523-1:2001 has the status ofa British Standard ICs 31.200; 35.240.50 BS EN IEC 61523-1 12002 61523-1 12001 Wk present to the responsible European committe
2、e any enquiries on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. - A list of organizations represented on this committee can be obtained on request to its secretary. From 1 Janua
3、ry 1997, all IEC publications have the number 60000 added to the old number. For instance, IEC 27-1 has been renumbered as IEC 60027-1. For a periodoftime during the change from one system to the other, publications may contain identifiers from both systems. Cr oss-r e fer enc e s The British Standa
4、rds which implement international or European publications referred to in this document may be found in the BSI Standards Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Find” facility of the BSI Standards Electronic Catalogue. A British Standard
5、 does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover, an
6、inside front cover, the EN title page, the EN foreword page, pages 1 to 423 and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. O BSI 8 March 2002 ISBN O 580 391 14 O EUROPEAN STANDARD EN 61523-1 NORME EUROPENNE EUROPISCHE NORM Januaw 2002
7、 ICs 35.240.50 English version Delay and power calculation standards Part 1 : Integrated circuit delay and power calculation systems (IEC 61 523-1 12001) Normes de calculs de puissance et de temps de retard Partie 1 : Systmes de calcul de puissance et de temps de retard des circuits intgrs (CE1 6152
8、3-1 12001) Berechnung von Verzgerung und Leistungsaufnahme beim Entwurf von Chips Teil 1: System zur Berechnung von Verzgerung und Leistu ngsaufna hme integrierter Schaltkreise (IC) (IEC 61523-1 12001) This European Standard was approved by CENELEC on 2001-12-04. CENELEC members are bound to comply
9、with the CENKENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secreta
10、riat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the
11、 official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European
12、Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels O 2002 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for C
13、ENELEC members. Ref. No. EN 61523-1:2002 E EN 61523-12002 Foreword The text of document 93/143/FDIS, future edition 1 of IEC 61 523-1, prepared by IEC TC 93, Design automation, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61523-1 on 2001-12-04. The following dates
14、 were fixed: - latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement - latest date by which the national standards conflicting with the EN have to be withdrawn (dop) 2002-09-01 (dow) 2004-12-01 This standard is based on
15、 IEEE Std P1481:1999; IEEE Standard for delay and power calculation system s. En dorse ment not i ce The text of the International Standard IEC 61 523-1 :2001 was approved by CENELEC as a European Standard without any modification. O BSI 8 March 2002 O BSI 8 March 2002 Page 1 EN 61523-1:2002 Page 2
16、EN 61523-1:2002 Contents SECTION PAGE 1. Overview 13 1.1 Scope 13 1.2 Purpose . 13 1.3 Contents of this standard . 14 2. References . 15 3. Definitions . 16 Acronyms and abbreviations 24 Delay and power calculation system architecture. 25 5.1 Overview . 25 5.2 Procedural interface . 26 5.2.1 Global
17、policies and conventions 26 5.2.2 Flow of control . 27 DPCM . application relationships 5.3.1 Technology library . 5.3.2 Subrule. . . 4. 5. 5.3 5.4 Inter-operability 28 Delay Calculation Language (DCL) 29 6. 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Character set. . Lexical elements . 30 6.2.1 Whitespace.
18、 30 6.2.2 Comments . 30 6.2.3 Tokens 6.2.5 Preprocessing directives . Name spaces of identifiers. . Storage durations of objects. Scope of identifiers . Linkages of identifiers . 41 41 42 . 6.6.2 IMPORT . 6.6.3 FORWARD. . 6.6.4 Chaining of E 42 DCL data types. 6.7.1 Native data types 42 42 6.7.2 Arr
19、ayypes . . 6.8.2 Explicit conversions . 46 Operators . 46 6.9.1 String prefix operator. . 47 6.9.2 Assignment operator . 6.9.3 New operator . O BSI 8 March 2002 Page 3 EN 61523-1:2002 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.9.4 SCOPE operator 6.9.5 Purity operator. 6.9.6 Timing propagation . 6.9.7
20、 Timing checks . . 6.9.8 Test mode operators. . 49 . 51 . 51 . 52 6.10.3 Assign variable 53 6.10.7 Pin range . 56 Computation order . 59 6.1 1.1 Mathematical expressions . 6.1 1.2 Logical expressions 6.1 1.3 Passed parameters . 60 6.1 1.4 WHEN clause . . 60 . 60 DCL statements . 60 6.12.1 Clauses .
21、60 6.12.2 Modifiers 6.12.3 Prototype . 68 6.12.6 Calculation statements 6.12.7 METHOD statement 73 Tables 6.13.1 TABLEDEF statement . 6.13.2 Table visibility rules . 76 6.13.3 TABLE statement . 77 6.13.4 Static tables . . 77 6.13.5 Dynamic tables 79 6.13.6 Dynamic table manipulation 80 6.13.7 Loolni
22、p table . Library control statements 6.14.2 SUBRULE statement . 87 6.14.3 SUBRULES statement . 89 91 Modeling . 92 6.15.1 Model organization 6.15.3 SUBMODEL statement. . 95 6.15.4 Modeling statements . 95 EmbeddedCcode . . 112 Definition of a subrule. . . 112 7. Power modeling and calculation. . 114
23、 7.1 Poweroverview . 115 7.2 Caching state information . 116 7.2.1 Initializing the state cache 116 O BSI 8 March 2002 Page 4 EN 61523-12002 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.2.2 State cache lifetime 116 Caching load and slew information 7.3.1 Loading the load and slew cache. 7.3.2 Load and sl
24、ew cach Simultaneous switching events . 117 Partial swing events 118 Power calculation. . 118 Accumulation of power consumption by the design . 120 Group pin list syntax and semantics . . 120 7.8.1 Syntax 7.8.2 Semantics. . 7.9.2 Semantics. . 122 7.9.3 Example . Sensitivity list syntax and semantics
25、 123 123 123 . 124 7.11.1 Syntax . . 124 7.1 1.2 Semantics. . 7.11.3 7.11.4 Condition expression operator precedence . 126 Condition expressions referencing pin states and transitions . 127 7.11.5 Semantics of nonexistent pins 127 8. Procedural Interface (PI). . 129 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 1
26、29 8.1.2 Application . 129 8.1.3 libdcmlr . 129 Control and data flow. . 130 Architectural requirements. . 8.4.2 Data cache guidelines for the DPCM . 131 ApplicatiodDPCM interaction . 131 8.5.1 Application initializes . 131 8.5.2 Application loads and initializes the DPCM . 131 8.5.3 8.5.4 Model dom
27、ain issues . 8.5.5 8.5.6 8.5.7 Re-entry requirements . 134 Application responsibilities when using a DPC 8.7.1 Standard structure rules. 8.7.2 User object registration 8.7.3 Selection of early and late slew values 134 Application use of the DPCM 136 8.8.1 Initialization of the D . . 136 8.8.2 Use of
28、 the DPCM . 137 Application requests timing models for cell instances . DPCM invokes application modeling callback functions 132 Application requests propagation delay . 133 DPCM calls application EXTERNAL functions. 134 O BSI 8 March 2002 Page 5 EN 61523-12002 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16
29、 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 DPCM library organization . 8.9.1 Multiple technolog . DPCM error handling. . 8.9.2 Model names . C level language for EXPOSE and EXTERNAL 8.11.1 Integer return code. . 8.11.2 . 139 The Standard Structure pointer 8.1 1.4 Passed arguments. . . 1
30、40 8.1 1.5 DCL array indexing. . . 141 . 141 8.1 1.7 include files . 141 PIN and BLOCK data structure requirements . DCM-STD-STRUCT Standard Structure. 8.13.2 Reserved fields . 8.13.3 Standard Structure value res 146 DCMTransmittedInfo structure Environment or user variables . PI functions summary .
31、 . 8.16.1 Expose functio . 8.16.3 Implicit functions. . . 152 8.16.4 PI function table description . . 155 PI function descriptions . 150 157 8.17.1 8.17.2 8.17.4 Interconnect loading related functions . Interconnect delay related functions Functions exporting limit information. 187 8.17.5 Functions
32、 gettinglsetting model information . 189 8.17.6 Functions importing instance name informat . 200 8.17.7 Process information functions. . 8.17.8 8.17.9 Power related functi Miscellaneous standard interface functions. 8.17.10 Array manipulation . 226 8.17.11 Initialization functions. . . 230 8.17.12 C
33、alculation fumtions. . 241 8.17.13 Modeling functions 86 Standard structure (dcms td-s tru. h) file Standard macros (dcmstd-macs.h) file . Standard loading (dcm1oad.h) file . . Standard debug (dcmdebug.h) file. . Standard platform-dependency (dcmp1tfm.h) file . Standard table descriptor(dcmutab.h) .
34、 313 Standard interface structures . 281 . 283 Standard array (dcmgarray.h) file DCM user array defines (dcmuarray.h) file. Standard state variables (dcmstate.h) file . 9. Parasitics . 314 9.1 Introduction 315 Targeted applications for SPEF . 3 15 9.2 O BSI 8 March 2002 Page 6 EN 61523-1:2002 9.3 SP
35、EF specification. . 9.3.1 Grammar . 315 9.3.2 File syntax 317 9.3.4 Comments . 325 9.3.5 File semant . 325 9.4 Examples . 341 9.4.1 Basic DNET file . 341 344 9.4.4 9.4.5 R-NET wi DNET with triplet par-value. 9.4.6 Merging SPEF files . 351 10. Physicaldesignexchange 357 10.1 Introduction . . 358 . 35
36、8 10.1.2 Targeted applications. 358 10.2 PDEF specification 359 10.2.1 PDEF grammar 359 10.2.2 PDEF file syntax . Comments within a PDEF file. 10.2.3 10.2.5 PDEF file semantics . 368 10.2.6 Attributes 379 10.3 Examples 399 10.3.1 Escaping 10.3.2 Clusters 10.3.3 Global routing . 404 10.3.4 Symbolic p
37、lacement constraints using PDEF . 405 A. Implementation requirements. . 408 Calculation of total load capacitance in the DPCS . 410 B. C. HoldControl 413 D. Bibliography 418 O BSI 8 March 2002 Page 7 EN 61523-12002 List of Figures FIGURE PAGE 5-1 5 -2 8-1 8-2 8-3 8 -4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8
38、-12 9- 1 10-1 10-2 10-3 10-4 10-5 10-6 10-7 c. 1 c.2 c.3 c.4 c.5 C.6 High-level DPCS architecture High-level DPCS architecture linkage structure DPCM/application procedural i PINandPINLIST . 143 PI function table example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39、 . . . . . . . . . . . 156 Parallel drivers example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Capacitance value example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Passed and
40、receiver p Integer LSB example Bias calculation. . . . Clockseparation 245 Differentedges . 246 Sample MODELPROC results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Additional MODELPROC results. . . . . . . . . . . . . . . . . . . . . . . . . . .
41、 . . . . . . . . . . . . . . . . . . 255 SPEF targeted applications PDEF targeted applications Hierarchical routes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Clusters cross logic hierarchy . . . . . . . . . . . . . . . . . . .
42、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Illustration of the chip used in the example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Aglobalroute 405 Symbolic cell and cluster placement Symbolic pin and net placement Transparent latch pair feedback
43、 Overlapperiod 414 Paddingthepaths . 415 Stable overlap period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Hold Control modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44、. . 416 Snipped feedback line 417 O BSI 8 March 2002 Page 8 EN 61523-12002 List of Tables TABLE 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 7- 1 7-2 7-3 7-4 8- 1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 9- 1 9-2 10-1 10-2 10-3
45、10-4 PAGE Keywords . . 32 DCL predefined references to Standard Structure fields . 33 DCL compiler generated predefined identifiers 37 Edge types and conversions . 38 . 39 TEST-TYPE conversions . 39 . 44 48 48 . 54 . 59 59 Calculation mode conversions. Test mode operato Logical operators. . . 56 Mat
46、hematical operator precedence (high to low Logical operator precedence (high to low) PinName-Identifier semantics PinNameLevel semantics . 126 PinName-State semantics 126 Condition expression operators. 127 Interaction between multiple technologies and application . . 139 Return code most significan
47、t byte. . 140 Return code least significant bytes . Data types defined in DCL and C 141 Header files . Predefined macro names . 143 . 146 EXPOSE functions . 147 EXTERNAL functions libdcmlr functions 152 Run-time library . 153 Calculation functions. 155 . 155 Modeling functions . Standard Structure f
48、ield semantics . 156 Maskencoding Mode propagation o 248 Mode operator enumerators for check . Enumeration pairs . 249 Edge propagation communication with DPCM Design flow values conn-attr types . Netlist type identifiers Design flow identifiers 370 Gate type attributes Validity of predefined identi
49、fiers for STORE clause . . 249 . 251 369 381 . 382 . O BSI 8 March 2002 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 Page 9 EN 61523-12002 Pin and gate-pin attributes 384 Nodetypeattributes 385 Nettypeattributes . 387 Net restriction attributes 388 Route restriction attributes 388 Route connectivity attributes . 389 Cluster restriction attributes . 391 Cluster connectivity attributes 394 Cell type attributes . 395 Cell restriction attributes 396 Pbus and nbus type attributes 398 Pnettypeattributes 398 Pnet restricti
