1、BRITISH STANDARD Behavioural languages - Part 3-3: Synthesis in VHDL The European Standard EN 61691-3-3:2001 has the status of a British Standard ICs 35.240.50 BS EN IEC 61691-3-3:2002 61691-3-3:2001 Wk present to the responsible European committee any enquiries on the interpretation, or proposals f
2、or change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. - A list of organizations represented on this committee can be obtained on request to its secretary. From 1 January 1997, all IEC publications have the number 60000 a
3、dded to the old number. For instance, IEC 27 has been renumbered as IEC 60027-1. For a period of time during the change over from one numbering system to the other, publications may contain identifiers from both systems. Cross-references The British Standards which implement these international or E
4、uropean publications may be found in the BSI Standards Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Find” facility of the BSI Standards Electronic Catalogue. A British Standard does not purport to include all the necessary provisions of a cont
5、ract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover, an inside front cover, the EN title page, pages 2 to 47, and a back co
6、ver. The BSI copyright date displayed in this document indicates when the document was last issued. O BSI 8 March 2002 ISBN O 580 39087 X EUROPEAN STANDARD EN 61691-3-3 NORME EUROPENNE EUROPISCHE NORM December 2001 ICs 35.240.50 English version Behavioural languages Part 3-3: Synthesis in VHDL (IEC
7、6 1 691 -3-31200 1 ) Langages relatifs au comportement Partie 3-3: Synthse en VHDL de la norme IEEE - Progiciels (CE1 61691-3-312001) Verhaltensebenensprache Teil 3-3: Synthese mit VHDL (I EC 61 691 -3-312001 ) This European Standard was approved by CENELEC on 2001-09-01. CENELEC members are bound t
8、o comply with the CENKENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Centra
9、l Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same stat
10、us as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC
11、European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels O 2001 CENELEC - All rights of exploitation in any form and by any means reserved worldw
12、ide for CENELEC members. Ref. No. EN 61691-3-3:2001 E Page 2 EN 61691-3-32001 Foreword The text of document 93/132/FDIS, future edition 1 of IEC 61691-3-3, prepared by IEC TC 93, Design automation, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61 691 -3-3 on 2001 -
13、09-01. The following dates were fixed: - latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement - latest date by which the national standards conflicting with the EN have to be withdrawn This standard is based on IEEE St
14、d 1076-3:1997, Synthesis packages. (dop) 2002-06-01 (dow) 2004-09-01 Endorse ment not ice The text of the International Standard IEC 61691-3-3:2001 was approved by CENELEC as a European Standard without any modification. O BSI 8 March 2002 Page 3 EN 61691-3-32001 I NTROD U CTIO N This standard, 6169
15、1 -3-3, supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. This standard includes package bodies, as described in annex A, which are availab
16、le in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store. O BSI 8 March 2002 Page 4 EN 61691-3-32001 BEHAVIOURAL LANGUAGES - Part 3-3: Synthesis in VHDL 1. Overview 1.1 Scope This standard defines standard practices for synthesizing bin
17、ary digital electronic circuits from VHDL source code. It includes the following: a) The hardware interpretation of values belonging to the BIT and BOOLEAN types defined by IEEE Std 1076-1993l and to the STD-ULOGIC type defined by IEEE Std 1164-1993. b) A function (STDMATCH) that provides “dont care
18、“ or “wild card“ testing of values based on the STD-ULOGIC type. c) Standard functions for representing sensitivity to the edge of a signal. d) Two packages that define vector types for representing signed and unsigned arithmetic values, and that define arithmetic, shift, and type conversion operati
19、ons on those types. This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2. 1.2 Terminology The word shall indicates mandatory requirements strictly to be followed in order
20、to conform to the standard and from which no deviation is permitted (shall equals is required to). The word should is used to indicate that a certain course of action is preferred but not necessarily required; or that (in the negative form) a cer- tain course of action is deprecated but not prohibit
21、ed (should equals is recommended that). The word may indicates a course of action permissible within the limits of the standard (may equals ispermittea?. A synthesis tool is said to accept a VHDL construct if it allows that construct to be legal input; it is said to interpret the construct (or to pr
22、ovide an interpretation of the construct) by producing something that repre- sents the construct. A synthesis tool is not required to provide an interpretation for every construct that it accepts, but only for those for which an interpretation is specified by this standard. Information on references
23、 can be found in Clause 2 O BSI 8 March 2002 Page 5 EN 61691-3-32001 1.3 Conventions This standard uses the following conventions: The body of the text of this standard uses boldface to denote VHDL reserved words (such as downto) and upper case to denote all other VHDL identifiers (such as REVERSE-R
24、ANGE or FOO). The text of the VHDL packages defined by this standard, as well as the text of VHDL examples and code fragments, is represented in a fixed-width font. All such text represents VHDL reserved words as lower case text and all other VHDL identifiers as upper case text. In the body of the t
25、ext, italics denote words or phrases that are being defined by the paragraph in which they occur. VHDL code fragments not supported by this standard are denoted by an italic fixed-width font. 2. References This standard shall be used in conjunction with the following publications. When the following
26、 standards are superseded by an approved revision, the revision shall apply. IEEE Std 1076-1993, IEEE Standard VHDL Language Reference Manual (ANSI)? IEEE Std 1164-1993, IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std-logic-1164) (ANSI). 3. Definitions Terms used in this s
27、tandard, but not defined in this clause, are assumed to be from IEEE Std 1076-1993 and IEEE Std 1164-1993. 3.1 argument: An expression occurring as the actual value in a function call or procedure call. 3.2 arithmetic operation: An operation for which the VHDL operator is +, -, *, I, mod, rem, abs,
28、or *. 3.3 assignment reference: The occurrence of a literal or other expression as the waveform element of a sig- nal assignment statement or as the right-hand side expression of a variable assignment statement. 3.4 dont care value: The enumeration literal - of the type STD-ULOGIC defined by IEEE St
29、d 1164- 1993. 3.5 equality relation: A VHDL relational expression in which the relational operator is =. 3.6 high-impedance value: The enumeration literal Z of the type STD-ULOGIC defined by IEEE Std 11 64- 1993. 3.7 inequality relation: A VHDL relational expression in which the relational operator
30、is I=. 3.8 logical operation: An operation for which the VHDL operator is and, or, nand, nor, xor, xnor, or not. 3.9 metalogical value: One of the enumeration literals U, X, W, or - of the type STD-ULOGIC defined by IEEE Std 1164-1993. 21EEE publications are available from the Institute of Electrica
31、l and Electronics Engineers, 445 Hoes Lane, P.O. Box 1331, Piscaaway, NJ08855-1331, USA. O BSI 8 March 2002 Page 6 EN 61691-3-32001 3.10 ordering relation: A VHDL relational expression in which the relational operator is , or =, 3.11 shift operation: An operation for which the VHDL operator is sll,
32、srl, sla, Sra, rol, or ror. 3.12 standard logic type: The type STD-ULOGIC defined by IEEE Std 1164-1993, or any type derived from it, including, in particular, one-dimensional arrays of STD-ULOGIC or of one of its subtypes. 3.13 synthesis tool: Any system, process, or tool that interprets VHDL sourc
33、e code as a description of an electronic circuit in accordance with the terms of this standard and derives an alternate description of that circuit. 3.14 user: A person, system, process, or tool that generates the VHDL source code that a synthesis tool pro- cesses. 3.15 vector: A one-dimensional arr
34、ay. 3.16 well-defined: Containing no metalogical or high-impedance element values. 4. Interpretation of the standard logic types This clause defines how a synthesis tool shall interpret values of the standard logic types defined by IEEE Std 1164-1993 and of the BIT and BOOLEAN types defined by IEEE
35、Std 1076-1993. Simulation tools, however, shall continue to interpret these values according to the standards in which the values are defined. 4.1 The STD-LOGIC-1164 values IEEE Std 11 64-1 993 defines the standard logic type: Uninitialized Forcing Unknown Forcing O Forcing 1 High Impedance Weak Unk
36、nown Weak O Weak 1 Dont care The logical values l, H, O, and L are interpreted as representing one of two logic levels, where each logic level represents one of two distinct voltage ranges in the circuit to be synthesized. IEEE Std 11 64-1 993 also defines a resolution function named RESOLVED and a
37、subtype STD-LOGIC that is derived from STD-ULOGIC by using RESOLVED. The resolution function RESOLVED treats the values O and 1 as forcing values that override the weak values L and H when multiple sources drive the same signal. The values U, X, W, and - are metalogical values; they define the behav
38、ior of the model itself rather than the behavior of the hardware being synthesized. The value U represents the value of an object before it is explicitly assigned a value during simulation; the values X and W represent forcing and weak values, respectively, for which the model is not able to disting
39、uish between logic levels. The value - is also called the don t care value. This standard treats it in the same way as the other metalog- ical values except when it is furnished as an argument to the STDMATCH functions in the O BSI 8 March 2002 Page 7 EN 61691-3-32001 1EEE.NLTMERIC-STD package. The
40、STDMATCH functions use - to implement a “match all” or “wild card” matching. The value Z is called the high-impedance value, and represents the condition of a signal source when that source makes no effective contribution to the resolved value of the signal. 4.2 Static constant values Wherever a syn
41、thesis tool accepts a reference to a locally static or globally static named constant, it shall treat that constant as the equivalent of the associated static expression. 4.3 Interpretation of logic values This subclause describes the interpretations of logic values occurring as literals (or in lite
42、rals) after a synthe- sis tool has replaced named constants by their corresponding values. 4.3.1 Interpretation of the forcing and weak values (O, I, L, H, FALSE, TRUE) A synthesis tool shall interpret the following values as representing a logic value O: The BIT value O. The BOOLEAN value FALSE. Th
43、e STD-ULOGIC values O and L It shall interpret the following values as representing a logic value 1 : The BIT value 1. The BOOLEAN value TRUE. The STD-ULOGIC value 1 and H. This standard makes no restriction as to the interpretation of the relative strength of values. 4.3.2 Interpretation of the met
44、alogical values (U, W, X, -) 4.3.2.1 Metalogical values in relational expressions If the VHDL source code includes an equality relation (=) for which one operand is a static metalogical value and for which the other operand is not a static value, a synthesis tool shall interpret the equality rela- t
45、ion as equivalent to the BOOLEAN value FALSE. If one operand of an equality relation is a vector, and one element of that vector is a static metalogical value, a synthesis tool shall interpret the entire equality relation as equivalent to the BOOLEAN value FALSE. A synthesis tool shall interpret an
46、inequality relation (i=) for which one operand is or contains a static meta- logical value, and for which the other operand is not a static value, as equivalent to the BOOLEAN value TRUE. A synthesis tool shall treat an ordering relation for which at least one operand is or contains a static metalog
47、- ical value as an error. 4.3.2.2 Metalogical values as a choice in a case statement If a metalogical value occurs as a choice, or as an element of a choice, in a case statement that is interpreted by a synthesis tool, the synthesis tool shall interpret the choice as one that can never occur. That i
48、s, the inter- O BSI 8 March 2002 Page 8 EN 61691-3-32001 pretation that is generated is not required to contain any constructs corresponding to the presence or absence of the sequence of statements associated with the choice. Whenever a synthesis tool interprets a case statement alternative that ass
49、ociates multiple choices with a sin- gle sequence of statements, it shall produce an interpretation consistent with associating the sequence of statements with each choice individually. Whenever a synthesis tool interprets a selected signal assignment statement, it shall interpret the selected signal assignment statement as if it were the case statement in the equivalent process as defined by IEEE Std 1076- 1993. 4.3.2.3 Metalogical values in logical, arithmetic, and shift operations
