1、9 3400855 0332909 692 EUROPEAN ir 1 ELECOMMUNICATION STANDARD ETS 300 462-5 September 1996 Source: ETSI TC-TM Reference: DWM-03017-5 ICs: 33.080 Key words: synchronization, timing, transmission Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5: Timing char
2、acteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment ETSI European Telecommunications Standards Institute ETSI Secretariat Postal address: F-O6921 Sophia Antipolis CEDEX - FRANCE Office address: 650 Route des Lucioles - Sophia Antipolis - Valbonne - FRA
3、NCE X.400: c=fr, a=atlas, p=etsi, s=secretariat - Internet: secretariat I et.s.fr Tel.: +33 92 94 42 O0 - Fax: +33 93 65 47 16 Copyright Notification: No part may be reproduced except as authorized by written permission. The copyright and the foregoing restriction extend to reproduction in all media
4、. O European Telecommunications Standards Institute 1996. All rights reserved. ETSI ETS*300*462- 5 9b 3400855 OL329LO 304 = Page 2 ETS 300 462-5: September 1996 Whilst every care has been taken in the preparation and publication of this document, errors in content, typographical or otherwise, may oc
5、cur. If you have comments concerning its accuracy, please write to “ETSI Editing and Committee Support Dept.“ at the address shown on the title page. ETSI ETS*300*462- 5 96 m 3Y00855 0132911 240 = Page 3 ETS 300 462-5: September 1996 Contents Foreword 1 2 3 4 5 6 7 a 9 10 Scope 7 Normative reference
6、s 7 Definitions. symbols and abbreviations . 8 3.1 Definitions 8 3.2 Abbreviations . 8 Frequency accuracy 8 Pull-in and pull-out ranges . 8 Noise generation . 8 6.1 Wander in locked mode . 8 6.2 Non-locked wander 10 6.3 Jitter . 10 Output jitter at a 2 048 kHz and 2 048 kbiffs interface 10 Output ji
7、tter at a Synchronous Transport Module N (STM-N) interface 10 6.3.1 6.3.2 Noise tolerance . 11 7.1 Jitter tolerance . 11 7.2 Wander tolerance 12 Transfer characteristic . 13 Transient response and holdover performance 14 9.1 Short-term phase transient response 14 9.2 Long-term phase transient respon
8、se (holdover) 15 9.3 Phase response to input signal interruptions . 16 9.4 Phase discontinuity 16 Interfaces . 16 Annex A (informative): Considerations on bandwidth requirements . 17 A.l Introduction 17 A.2 Relevant network requirements and assumptions 17 A.2.1 A.2.2 A.2.3 ITU-T Recommendation G.825
9、 STM-N jitter acceptance 17 Wander accumulation in a synchronization distribution chain . 17 Phase transients due to automatic timing restoration 18 A.3 Conclusion . 19 Annex B (informative): Measurement methods for transfer characteristics 20 B.l Phase step response . 20 8.2 Frequency step response
10、 21 8.3 Sinusoidal phase response . 22 6.4 White phase noise response (frequency domain) . 22 ETSI ETS*300*462- 5 96 = 3400855 CIL32712 187 Page 4 ETS 300 462-5: September 1996 B.5 White phase noise response (time domain) . 23 Annex C (informative): Information on the SEC noise model . 24 Annex D (i
11、nformative): Bibliography . 25 History . 26 ETSI ETS*300*4b2- 5 9b 3V00855 OL32913 013 Page 5 ETS 300 462-5: September 1996 Foreword This European Telecommunication Standard (ETS) has been produced by the Transmission and Multiplexing (TM) Technical Committee of the European Telecommunications Stand
12、ards Institute (ETSI). This ETS provides requirements for synchronization networks that are compatible with the performance requirements of digital networks. This ETS consists of 6 parts as follows: Part i: “Definitions and terminology for synchronization networks“ (ETS 300 462-1 ). Part 2: “Synchro
13、nisation network architecture“ (ETS 300 462-2). Part 3: Part 4: Part 5: “The control of jitter and wander within synchronization networks“ (ETS 300 462-3). “Timing characteristics of slave clocks suitable for synchronization supply to Synchronous Digital Hierarchy (SDH) and Plesiochronous Digital Hi
14、erarchy (PDH) equipment“ (ETS 300 462-4). “Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment“. Part 6: “Timing characteristics of primary reference clocks“ (ETS 300 462-6). NOTE: Parts 4 and 6 of this ETS are being developed by STC TM 3 an
15、d are not yet available. Transposition dates Date of adoption of this ETS: Date of latest announcement of this ETS (doa): 16 August 1996 31 December 1996 Date of latest publication of new National Standard or endorsement of this ETS (dop/e): 30 June 1997 I I Date of withdrawal of any conflicting Nat
16、ional Standard (dow): 30 June 1997 ETSI ETS*300*462- 5 96 = 3400655 0132914 T5T W Page 6 ETS 300 462-5: September 1996 Blank page ETSI ETS*300*4b2- 5 9b = 3Y00855 0132715 77b Page 7 ETS 300 462-5: September 1996 1 Scope This European Telecommunication Standard (ETS) outlines requirements for timing
17、devices used in synchronising network equipment that operates according to the principles governed by the Synchronous Digital Hierarchy (SDH). These requirements apply under the normal environmental conditions specified for SDH equipment. Typical SDH equipment contains a slave clock linked to a mast
18、er, or a primary reference clock. The logical function of the SEC is described in figure 2 of ETS 300 462-2 3. In general the SDH Equipment Clock (SEC) will have multiple reference inputs. In the event that all links between the master and the slave clock fail, the equipment should be capable of mai
19、ntaining operation (holdover) within the prescribed performance limits contained within this ETS. Slave clocks used in SDH equipment shall meet specific requirements in order to comply with the jitter specifications given in ETS 300 417-1 -1 9 for plesiochronous tributaries. The case where clock per
20、formance is required in SDH equipment is outside the scope of this ETS.This is currently under study as part 4 of this ETC as described in the Foreword. 2 Normative references This ETS incorporates by dated or undated reference, provisions from other publications. These normative references are cite
21、d at the appropriate places in the text and the publications are listed hereafter. For dated references subsequent amendments to, or revisions of, any of these publications apply to this ETS only when incorporated in it by amendments or revisions. For undated references the latest edition of the pub
22、lication referred to applies. 131 41 151 ETS 300 O1 9: “Equipment Engineering (EE); Environmental conditions and environmental tests for telecommunications equipment“. prETS 300 462-1 : “Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 1 : Definitions and t
23、erminology for synchronization networks“. prETS 300 462-2: “Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 2: Synchronisation network architecture“. ITU-T Recommendation G.823: “The control of jitter and wander within digital networks which are based on t
24、he 2 048 kbit/s hierarchy“. prETS 300 462-6: “Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 6: Timing characteristics of primary reference clocks“. ITU-T Recommendation G.703: “PhysicaVelectricaI characteristics of hierarchical digital interfaces“. ITU-T
25、 Recommendation G.825: “The control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (SDH)“. ITU-T Recommendation Q.551: “Transmission characteristics of digital exchanges“. ETS 300 417-1-1 (1 996): “Transmission and Multiplexing (TM); Generic functio
26、nal requirements for Synchronous Digital Hierarchy (SDH) equipment; Part 1-1 : Generic processes and performance“. Page 8 ETSI ETS*300*4bZ- 5 76 = 3400855 0332936 822 m ETC 300 462-5: September 1996 3 Definitions, symbols and abbreviations 3.1 Definitions For the purposes of this ETS, the definition
27、s given in ETC 300 462-1 2 apply. 3.2 Abbreviations For the purposes of this ETS, the following abbreviations apply: ITU-T MTIE NE PDH PLL PPm PRC SDH SEC ssu STM-N TDEV UI UlPP VCO International Telecommunications Union-Telecommunications sector Maximum Time Interval Error Network Element Plesiochr
28、onous Digital Hierarchy Phase Locked Loop parts per million Primary Reference Clock Synchronous Digital Hierarchy SDH Equipment Clock Synchronisation Supply Unit Synchronous Transport Module N Time Deviation Unit Interval Unit Interval peak to peak Voltage Controlled Oscillator A full list of abbrev
29、iations used in timing and synchronization is listed in ETS 300 462-1 2. 4 Frequency accuracy Under free-running conditions, the SEC output frequency accuracy shall be within 4,6 pprn with regard to a reference traceable to a clock as specified in ETS 300 462-6 5. NOTE: The time interval for this ac
30、curacy specification is for further study. 5 Pull-in and pull-out ranges The minimum pull-in range shall be f 4,6 ppm, whatever the internal oscillator frequency offset may be. The Pull-out range is for further study. A value of f 4,6 pprn has been proposed. 6 Noise generation The noise generation o
31、f a SEC represents the amount of phase noise produced at the output when there is an ideal input reference signal or the clock is in holdover state. A suitable reference, for practical testing purposes, implies a performance level at least 10 times more stable than the output requirements. The abili
32、ty of the clock to limit this noise is described by its frequency stability. The measures Maximum Time Interval Error (MTIE) and Time Deviation (TDEV) are useful for characterization of noise generation performance. MTIE and TDEV are measured through an equivalent 10 Hz, first order, low-pass measur
33、ement filter, at a maximum sampling time to of 1/30 second. The minimum measurement period for TDEV is twelve times the integration period (T = 12t). 6.1 Wander in locked mode When the SEC is in the locked mode of operation, the MTIE and TDEV measured using the synchronised clock configuration defin
34、ed in figure la of ETS 300 462-1 2 shall have the limits in tables 1 and 2, if the temperature is constant (k 1 K). Page 9 ETS 300 462-5: September 1996 ETSI ETS*300*4b2- 5 9b 3400855 0332937 769 = Table 1 : Wander in locked mode for constant temperature specified in MTIE . Requirement 40 ns 40 toli
35、 ns 25 t O* ns Observation interval 0,l 100s The resultant requirement is shown by the upper solid line in figure 2. Interface Measuring filter Peak-to-peak amplitude (Hz) (Ui) STM-1 500 to 1,3 M 0,50 65 k to 1,3 M 0,lO STM-4 1 kto5M 0,50 250 k to 5 M 0,lO STM-16 5 k to 20 M 0,50 1 Mto20M 0,l o 6.2
36、Non-locked wander When a clock is not locked to a synchronization reference, the random noise components are negligible compared to deterministic effects like initial frequency off set. Consequently the non-locked wander effects are included in subclause 9.1. 6.3 Jitter While most specifications in
37、this ETS are independent of the output interface at which they are measured, this is not the case for jitter production; jitter generation specifications shall utilize existing specifications that are currently specified differently for different interface rates. These requirements are stated separa
38、tely for the interfaces identified in clause 1 O. To be consistent with other jitter requirements the specifications are in Unit Interval peak to peak (Uipp), where the Unit Interval (Ui) corresponds to the reciprocal of the bit rate of the interface. NOTE: Due to the stochastic nature of jitter, th
39、e peak-to-peak values given in this clause eventually are exceeded. The requirements shall therefore be fulfilled with a probability of 99 %. 6.3.1 Output jitter at a 2 048 kHz and 2 048 kbis interface In the absence of input jitter, the intrinsic jitter at a 2 048 kHz or 2 048 kbis output interface
40、 as measured over a 60 seconds interval shall not exceed 0,05 Ulpp when measured through a band-pass filter with corner frequencies at 20 Hz and 100 kHz each with a first order 20 dB/decade roll-off characteristic. 6.3.2 Output jitter at a Synchronous Transport Module N (STM-N) interface In the abse
41、nce of input jitter at the synchronization interface, the intrinsic jitter at optical STM-N output interfaces as measured over a 60 seconds interval shall not exceed the limits given in table 4. The allowed jitter on an STM-1 electrical interface is for further study. Table 4: Output jitter requirem
42、ents for STM-N optical interfaces for STM-1: 1 UI = 6,43 ns; for STM-4: 1 UI = 1,61 ns; for STM-16: 1 UI = 0.40 ns. Page 11 ETS 300 462-5: September 1996 ETSI ETS*300*4b2- 5 7b 3400855 OL329L9 53L = Requirement 250 ns 4 900 f ns 100 ns 7 Noise tolerance Frequency intetval 1 15 s, exceed the followin
43、g limit: AT(S) = (a, + a2) s + 0,s b 2 + c where : NOTE 1: NOTE 2: NOTE 3: NOTE 4: al = 50 ns/s (see note 1); a2 = 2 O00 ns/s (see note 2); b = 1,16 x 10“ ns/s* (see note 3); C = 120 ns (see note 4). The frequency offset al represents an initial frequency offset corresponding to 5 x (0,05 PP). The f
44、requency offset a2 accounts for temperature variations after the clock went into holdover and corresponds to 2 x 10, (2 ppm). If there are no temperature variations, the term a2 S should not contribute to the phase error. The drift b is caused by ageing: 1,16 x ns/s2 corresponds to a frequency drift
45、 of 1 x lo* /day (0,Ol ppm/day). This value is derived from typical ageing characteristics after 10 days of continuous operation. It is not intended to measure this value on a per day basis as the temperature effect will dominate. The phase offset C takes care of any additional phase shift that may
46、arise during the transition at the entry of the holdover state. This limit is subject to a maximum frequency offset of f 4,6 ppm. The behaviour for S 1 In summary the requirements listed above lead to the following bandwidth constraints for the SEC in table A.l. distribution chain; SSU/SEClbandwidth
47、 ratio distribution chain; SEC accumulation timing restoration Wander accumulation in a synchronization 1 p maximum phase transients due to automatic Table A.l: SEC bandwidth constraints 1 1 From this it is concluded that the bandwidth of the SEC should be in the range 1 to 10 Hz. Parie 20 Phase Dev
48、iation ETSI ETS*300*462- 5 96 3400855 0332928 544 E 7 L ( AT 20X ,) /I i ET5 300 462-5: September 1996 Annex B (informative): Measurement methods for transfer characteristics To measure the transfer characteristics of the SEC several equivalent measurement methods are listed. The difficulty in measu
49、ring the phase transfer characteristic is that the (phase) signals that are transferred through the clock have to be substantially larger than the internally generated phase noise. This may require large input phase deviations, which may cause overflow of the phase detector or may throw the SEC into holdover. Such events would make the measurement worthless. Depending on the particular implementation of an SEC, different methods of measuring may be appropriate to measure the transfer characteristic. Relevant factors are the amount of internally generated phase noise,
