1、 ETSI TS 100 392-3-6 V1.1.1 (2003-12)Technical Specification Terrestrial Trunked Radio (TETRA);Voice plus Data (V+D);Part 3: Interworking at the Inter-System Interface (ISI);Sub-part 6: Speech format implementation forcircuit mode transmissionETSI ETSI TS 100 392-3-6 V1.1.1 (2003-12) 2 Reference DTS
2、/TETRA-03106 Keywords interworking, radio, TETRA, V+D ETSI 650 Route des Lucioles F-06921 Sophia Antipolis Cedex - FRANCE Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N 348 623 562 00017 - NAF 742 C Association but non lucratif enregistre la Sous-Prfecture de Grasse (06) N 7803/88 Important
3、notice Individual copies of the present document can be downloaded from: http:/www.etsi.org The present document may be made available in more than one electronic version or in print. In any case of existing or perceived difference in contents between such versions, the reference version is the Port
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5、n on the current status of this and other ETSI documents is available at http:/portal.etsi.org/tb/status/status.asp If you find errors in the present document, send your comment to: editoretsi.org Copyright Notification No part may be reproduced except as authorized by written permission. The copyri
6、ght and the foregoing restriction extend to reproduction in all media. European Telecommunications Standards Institute 2003. All rights reserved. DECTTM, PLUGTESTSTM and UMTSTM are Trade Marks of ETSI registered for the benefit of its Members. TIPHONTMand the TIPHON logo are Trade Marks currently be
7、ing registered by ETSI for the benefit of its Members. 3GPPTM is a Trade Mark of ETSI registered for the benefit of its Members and of the 3GPP Organizational Partners. ETSI ETSI TS 100 392-3-6 V1.1.1 (2003-12) 3 Contents Intellectual Property Rights4 Foreword.4 Introduction 5 1 Scope 6 2 References
8、 6 3 Definitions and abbreviations.6 3.1 Definitions6 3.2 Abbreviations .7 4 Overview of FSTE .7 4.1 Mapping structure of FSTE7 4.2 FSTE block layer8 4.3 TETRA ACELP .8 5 Block format and procedures for FSTE8 5.1 General requirements for FSTE8 5.2 FSTE block format .8 5.3 Block synchronization10 5.4
9、 Block error10 5.5 Control bits.11 5.6 Spare bits11 6 Overview of OSTE.11 6.1 Mapping structure of OSTE .11 6.2 OSTE block layer .12 6.3 TETRA ACELP .12 7 Block format and procedures for OSTE.13 7.1 General requirements .13 7.2 OSTE block format 13 7.3 Block synchronization16 7.4 Block error16 7.4.1
10、 General on block errors.16 7.4.2 Loss of synchronization16 7.4.3 Frame stealing.16 7.5 Control bits.17 7.6 Frame number bits17 7.7 Block end and idle bits .18 Annex A (informative): Support of circuit mode services 19 A.1 Background 19 A.2 Block format and procedures .19 A.2.1 Mapping structure.19
11、A.2.2 FSTE block format .20 A.2.3 Block synchronization22 A.2.4 Block error22 A.2.4.1 General on block errors.22 A.2.4.2 Loss of synchronization23 A.2.4.3 Frame stealing.23 A.2.5 Control bits.23 Annex B (informative): Bibliography.24 History 25 ETSI ETSI TS 100 392-3-6 V1.1.1 (2003-12) 4 Intellectua
12、l Property Rights IPRs essential or potentially essential to the present document may have been declared to ETSI. The information pertaining to these essential IPRs, if any, is publicly available for ETSI members and non-members, and can be found in ETSI SR 000 314: “Intellectual Property Rights (IP
13、Rs); Essential, or potentially Essential, IPRs notified to ETSI in respect of ETSI standards“, which is available from the ETSI Secretariat. Latest updates are available on the ETSI Web server (http:/webapp.etsi.org/IPR/home.asp). Pursuant to the ETSI IPR Policy, no investigation, including IPR sear
14、ches, has been carried out by ETSI. No guarantee can be given as to the existence of other IPRs not referenced in ETSI SR 000 314 (or the updates on the ETSI Web server) which are, or may be, or may become, essential to the present document. Foreword This Technical Specification (TS) has been produc
15、ed by ETSI Project Terrestrial Trunked Radio (TETRA). The present document is part 3, sub-part 6 of a multi-part deliverable covering Voice plus Data (V+D), as identified below: EN 300 392-1: “General network design“; EN 300 392-2: “Air Interface (AI)“; EN 300 392-3: “Interworking at the Inter-Syste
16、m Interface (ISI)“; EN 300 392-3-1: “General design“; EN 300 392-3-2: “Additional Network Feature Individual Call (ANF-ISIIC)“; EN 300 392-3-3: “Additional Network Feature Group Call (ANF-ISIGC)“; EN 300 392-3-4: “Additional Network Feature Short Data Service (ANF-ISISDS)“; EN 300 392-3-5: “Addition
17、al Network Feature for Mobility Management (ANF-ISIMM)“; TS 100 392-3-6: “Speech format implementation for circuit mode transmission“; TS 100 392-3-7: “Speech Format Implementation for Packet Mode Transmission“; ETS 300 392-4: “Gateways basic operation“; EN 300 392-5: “Peripheral Equipment Interface
18、 (PEI)“; EN 300 392-7: “Security“; EN 300 392-9: “General requirements for supplementary services“; EN 300 392-10: “Supplementary services stage 1“; EN 300 392-11: “Supplementary services stage 2“; EN 300 392-12: “Supplementary services stage 3“; ETS 300 392-13: “SDL model of the Air Interface (AI)“
19、; ETS 300 392-14: “Protocol Implementation Conformance Statement (PICS) proforma specification“. TS 100 392-15: “TETRA frequency bands, duplex spacings and channel numbering“; TS 100 392-16: “Network Performance Metrics“; TS 100 392-17: “TETRA V+D and DMO Release 1.1 specifications“. ETSI ETSI TS 10
20、0 392-3-6 V1.1.1 (2003-12) 5 Introduction There are two different speech format options defined for the TETRA InterSystem Interface (ISI) speech transmission one for circuit mode support and another for packet mode support. The two options allow different techniques in designing and interconnecting
21、TETRA SwMIs. Those based on packet mode transmission technology can use the complementary packet based option, and those based on circuit mode transmission technology can take advantage of the present subpart of the ISI. The reason for having two options shall be found in the nature of existing TETR
22、A SwMIs from various manufacturers. The existing SwMIs can generally be divided into two types: those that use packet switched technology and those which are using a circuit switched technology. When connecting a circuit switched SwMI to a packet switched SwMI there must be a conversion performed fr
23、om one technology to the other. When a circuit switched and a packet switched SwMI is connected, a TETRA ISI Transport Converter (ISI-TC) is required. The ISI-TC does not necessarily need to be provided by the SwMI manufactures. The location of the ISI-TC will be dependent on the backbone network th
24、at is used to interconnect the two systems. If a packet switched backbone is available, then the location of the ISI-TC is best in the circuit switched SwMI end. If a circuit switched backbone is available, then the location of the ISI-TC is best at the packet SwMI. ETSI ETSI TS 100 392-3-6 V1.1.1 (
25、2003-12) 6 1 Scope The present document specifies Speech Format Implementation for Circuit Mode Transmission in TETRA InterSystem Interface (ISI). The present document defines the format of user information that is transported between two SwMIs using the TETRA ISI and supporting circuit mode speech
26、transmission for ISI connections. It is complementary to the subpart of the ISI specification describing a packet mode approach. The present document covers how speech frames are coded/decoded within digital circuit mode connection (2Mbit/s; G.703/G.704). That is the primary transport layer between
27、those network elements within both SwMIs, which need to transfer/manipulate speech circuits. The present document provides two options for speech transport called First Speech Transport Encoding format and Optimized Speech Transport Encoding format. The present document does not cover any signalling
28、 issues (e.g. how speech circuits are reserved on the ISI interface, how call set-up is done). 2 References The following documents contain provisions which, through reference in this text, constitute provisions of the present document. References are either specific (identified by date of publicati
29、on and/or edition number or version number) or non-specific. For a specific reference, subsequent revisions do not apply. For a non-specific reference, the latest version applies. Referenced documents which are not found to be publicly available in the expected location might be found at http:/docbo
30、x.etsi.org/Reference. 1 ETSI ETS 300 395-2: “Terrestrial Trunked Radio (TETRA); Speech codec for full-rate traffic channel; Part 2: TETRA codec“. 3 Definitions and abbreviations 3.1 Definitions For the purposes of the present document, the following terms and definitions apply: C-stolen sub block: s
31、ub block stolen from speech or circuit mode data by a signalling message Mobile Station (MS): physical grouping that contains all of the mobile equipment that is used to obtain TETRA services NOTE: By definition, a mobile station contains at least one Mobile Radio Stack (MRS). U-stolen sub block: su
32、b block stolen from speech or circuit mode data by a user application and intended for user to user signalling ETSI ETSI TS 100 392-3-6 V1.1.1 (2003-12) 7 3.2 Abbreviations For the purposes of the present document, the following abbreviations apply: ACELP Algebraic CELP BFI Bad Frame Indicator FEC F
33、orward Error Correction FN Frame Number FSTE First Speech Transport Encoding format ISI Inter-System Interface MRS Mobile Radio Stack MS Mobile Station OSTE Optimized Speech Transport Encoding format STE Speech Transport Encoding format SwMI Switching and Management Infrastructure 4 Overview of FSTE
34、 4.1 Mapping structure of FSTE TETRA voice codec encoded audio (speech) is mapped into First Speech Transport Encoding format (FSTE) used for voice signal transmission between SwMIs, see figure 1. The TETRA speech encoding is defined in ETS 300 395-2 1 and the G.704 framing is defined in ITU-T Recom
35、mendation G.704. B3 B4 B1 B2 B7 1 timeslot = 8 bits (64 kbit/s circuit) 2 3 0 1 G.704 : 2M frame = 32 timeslots = 256 bits ( = 125 us ) (2 Mbit/s line) 4 B8 1 bit ( 8 kbit/s circuit) 1 2 3 479 480 N 31 1 STE block = 480 bits = 60 ms ( using 8 kbit/s circuit) 2 TETRA speech frames = 2 x 137 bits (net
36、 rate=4,567 kbit/s) Framing information 240 samples of speech (8 kHz) (30 ms) G.704STE A C E L P A U D I O 40 samples of “future“ Figure 1: Mapping structure for FSTE ETSI ETSI TS 100 392-3-6 V1.1.1 (2003-12) 8 4.2 FSTE block layer The TETRA speech frames are mapped to FSTE block format within 8 kbi
37、t/s circuit. Detailed specification of FSTE format is given on clause 5. Also an optimized block format can be used, which reduces the need for buffering due to 18th frame gap. The optimized block format is presented in clauses 6 and 7 of the present document. 4.3 TETRA ACELP Audio signal is coded w
38、ith TETRA ACELP coding. The TETRA ACELP coding is a TETRA speech coding standard ETS 300 395-2 1. TETRA ACELP coding produces 137 coding bits from 30 ms length of audio speech frame, which consists of 240 speech audio samples taken with 8 kHz rate. 5 Block format and procedures for FSTE 5.1 General
39、requirements for FSTE FSTE is the STE block format that shall be used to carry TETRA ACELP coded speech frames within 8 kbit/s circuits over the TETRA ISI fulfilling requirements of the present document. Each STE block shall incorporate block synchronization (clause 5.3), control bits (clause 5.5),
40、data bits (=speech) and eventually spare bits (clause 5.6). The details of the FSTE block format are described in clause 5.2. The STE blocks shall be transmitted as soon as available at 8 kbit/s on the physical link. Receiver process shall use block synchronization as defined in clause 5.3. Handling
41、 of block errors is described on clause 5.4. 5.2 FSTE block format The FSTE block shall be encoded as presented in table 1. The bits of the block shall be sent over 8 kbit/s channel in octet order so that the octet “0“ and its bit number “1“ is sent first. The meaning of different bits in the block
42、is: C = control bits (see clause 5.5) D = data bits (i.e. TETRA ACELP coded speech bits) S = spare bits SYNC_1 = synchronization bits with value “1“. ETSI ETSI TS 100 392-3-6 V1.1.1 (2003-12) 9 The FSTE block shall contain two sub-blocks as defined in clause 4.1. Table 1: FSTE block format Octet N 1
43、 2 3 4 5 6 7 8 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 4 1 C1 C2 C3 C4 C5 D1 D2 5 D3 D4 D5 D6 D7 D8 D9 D10 6 D11 D12 D13 D14 D15 D16 D17 D18 7 SYNC_1 D19 D20 D21 D22 D23 D24 D25 8 D26 D27 D28 D29 D30 D31 D32 D33 9 D34 D35 D36 D37 D38 D39 D40 D41 10 SYNC_1 D42 D43 D44 D45 D46 D47 D48 11
44、 D49 D50 D51 D52 D53 D54 D55 D56 12 D57 D58 D59 D60 D61 D62 D63 D64 13 SYNC_1 D65 D66 D67 D68 D69 D70 D71 14 D72 D73 D74 D75 D76 D77 D78 D79 15 D80 D81 D82 D83 D84 D85 D86 D87 16 SYNC_1 D88 D89 D90 D91 D92 D93 D94 17 D95 D96 D97 D98 D99 D100 D101 D102 18 D103 D104 D105 D106 D107 D108 D109 D110 19 SY
45、NC_1 D111 D112 D113 D114 D115 D116 D117 20 D118 D119 D120 D121 D122 D123 D124 D125 21 D126 D127 D128 D129 D130 D131 D132 D133 22 SYNC_1 D134 D135 D136 D137 S1 S2 S3 23 S4 S5 S6 S7 S8 S9 S10 S11 24 S12 S13 S14 S15 S16 S17 S18 S19 25 SYNC_1 S20 S21 S22 S23 S24 S25 S26 26 S27 S28 S29 S30 S31 S32 S33 S3
46、4 27 S35 S36 S37 S38 S39 S40 S41 S42 28 SYNC_1 S43 S44 S45 S46 S47 S48 S49 29 S50 S51 S52 S53 S54 S55 S56 S57 30 S58 S59 S60 S61 S62 S63 S64 S65 31 SYNC_1 S66 S67 S68 S69 S70 S71 S72 32 S73 S74 S75 S76 S77 S78 S79 D1 33 D2 D3 D4 D5 D6 D7 D8 D9 34 SYNC_1 D10 D11 D12 D13 D14 D15 D16 35 D17 D18 D19 D20
47、 D21 D22 D23 D24 36 D25 D26 D27 D28 D29 D30 D31 D32 37 SYNC_1 D33 D34 D35 D36 D37 D38 D39 38 D40 D41 D42 D43 D44 D45 D46 D47 39 D48 D49 D50 D51 D52 D53 D54 D55 40 SYNC_1 D56 D57 D58 D59 D60 D61 D62 41 D63 D64 D65 D66 D67 D68 D69 D70 42 D71 D72 D73 D74 D75 D76 D77 D78 43 SYNC_1 D79 D80 D81 D82 D83 D8
48、4 D85 44 D86 D87 D88 D89 D90 D91 D92 D93 45 D94 D95 D96 D97 D98 D99 D100 D101 46 SYNC_1 D102 D103 D104 D105 D106 D107 D108 47 D109 D110 D111 D112 D113 D114 D115 D116 48 D117 D118 D119 D120 D121 D122 D123 D124 49 SYNC_1 D125 D126 D127 D128 D129 D130 D131 50 D132 D133 D134 D135 D136 D137 S1 S2 51 S3 S
49、4 S5 S6 S7 S8 S9 S10 52 SYNC_1 S11 S12 S13 S14 S15 S16 S17 53 S18 S19 S20 S21 S22 S23 S24 S25 54 S26 S27 S28 S29 S30 S31 S32 S33 ETSI ETSI TS 100 392-3-6 V1.1.1 (2003-12) 10Octet N 1 2 3 4 5 6 7 8 55 SYNC_1 S34 S35 S36 S37 S38 S39 S40 56 S41 S42 S43 S44 S45 S46 S47 S48 57 S49 S50 S51 S52 S53 S54 S55 S56 58 SYNC_1 S57 S58 S59 S60 S61 S62 S63 59 S64 S65 S66 S67 S68 S69 S70 S71 60 S72 S73 S74 S75 S76 S77 S78 S79 5.3 Block synchronization During idle mode, when there is not any active call within that 8 kbit/s circuit, no block synchronization is done and the 8 kbit/
