1、 ETSI TS 102 694-2 V10.3.0 (2015-03) Smart Cards; Test specification for the Single Wire Protocol (SWP) interface; Part 2: UICC features (Release 10) TECHNICAL SPECIFICATION ETSI ETSI TS 102 694-2 V10.3.0 (2015-03)2Release 10Reference RTS/SCP-00SWPUva30 Keywords smart card, terminal ETSI 650 Route d
2、es Lucioles F-06921 Sophia Antipolis Cedex - FRANCE Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N 348 623 562 00017 - NAF 742 C Association but non lucratif enregistre la Sous-Prfecture de Grasse (06) N 7803/88 Important notice The present document can be downloaded from: http:/www.etsi.org
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6、Notification No part may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm except as authorized by written permission of ETSI. The content of the PDF version shall not be modified without the written authorization of ETSI. The copyr
7、ight and the foregoing restriction extend to reproduction in all media. European Telecommunications Standards Institute 2015. All rights reserved. DECTTM, PLUGTESTSTM, UMTSTMand the ETSI logo are Trade Marks of ETSI registered for the benefit of its Members. 3GPPTM and LTE are Trade Marks of ETSI re
8、gistered for the benefit of its Members and of the 3GPP Organizational Partners. GSM and the GSM logo are Trade Marks registered and owned by the GSM Association. ETSI ETSI TS 102 694-2 V10.3.0 (2015-03)3Release 10Contents Intellectual Property Rights 11g3Foreword . 11g3Modal verbs terminology 11g3I
9、ntroduction 11g31 Scope 12g32 References 12g32.1 Normative references . 12g32.2 Informative references 13g33 Definitions, symbols and abbreviations . 13g33.1 Definitions 13g33.2 Symbols 14g33.3 Abbreviations . 14g33.4 Formats . 15g33.4.1 Format of the table of optional features 15g33.4.2 Format of t
10、he applicability table . 15g33.4.3 Status and Notations . 15g34 Test environment 16g34.1 Table of optional features . 16g34.2 Applicability table 17g34.3 Information to be provided by the DUT supplier . 22g34.4 Test equipment . 22g34.4.1 Measurement/setting uncertainties 22g34.4.2 Default conditions
11、 for DUT operation 23g34.4.2.1 Temperature 23g34.4.2.2 ETSI TS 102 221 interface contacts (CLK, RST, I/O) and contact Vcc . 24g34.4.2.3 ETSI TS 102 600 interface contacts (IC_DP, IC_DM) . 24g34.4.2.4 ETSI TS 102 613 interface contact (SWIO) 25g34.4.2.5 Status of UICC interfaces 25g34.4.2.6 Character
12、istics of LLCs 25g34.4.2.6.1 ACT LLC 25g34.4.2.6.2 SHDLC LLC . 25g34.4.2.6.3 CLT LLC . 26g34.4.3 Minimum/maximum conditions for DUT operation . 26g34.4.3.1 Temperature 26g34.4.3.2 Contact Vcc. 26g34.5 Test execution 26g34.5.1 Parameter variations . 26g34.5.2 Execution requirements 26g34.6 Pass crite
13、rion 27g35 Test cases 27g35.1 Principle of the Single Wire Protocol . 27g35.2 System architecture 27g35.2.1 General overview 27g35.2.2 ETSI TS 102 221 support . 27g35.2.2.1 Conformance requirements . 27g35.2.3 Configurations 28g35.2.3.1 Conformance requirements . 28g35.2.3.2 Test case 1: Global Inte
14、rface bytes of the ATR 28g35.2.3.2.1 Test execution 28g35.2.3.2.2 Initial conditions 28g35.2.3.2.3 Test procedure . 28g35.2.3.3 Test case 2: interaction with ETSI TS 102 221 interface - SWP activation while the UICC receives data 28g35.2.3.3.1 Test execution 28g3ETSI ETSI TS 102 694-2 V10.3.0 (2015-
15、03)4Release 105.2.3.3.2 Initial conditions 28g35.2.3.3.3 Test procedure . 29g35.2.3.4 Test case 3: interaction with ETSI TS 102 221 interface - SWP activation while the UICC sends data 29g35.2.3.4.1 Test execution 29g35.2.3.4.2 Initial conditions 29g35.2.3.4.3 Test procedure . 29g35.2.4 Interaction
16、with other interfaces . 30g35.2.4.1 Conformance requirements . 30g35.2.4.2 Test case 1: interaction with ETSI TS 102 221 interface - ETSI TS 102 221 clock stop 30g35.2.4.2.1 Test execution 30g35.2.4.2.2 Initial conditions 30g35.2.4.2.3 Test procedure . 30g35.2.4.3 Test case 2: interaction with ETSI
17、TS 102 221 interface - ETSI TS 102 221 reset 30g35.2.4.3.1 Test execution 30g35.2.4.3.2 Initial conditions 30g35.2.4.3.3 Test procedure . 31g35.2.4.4 Test case 3: interaction with ETSI TS 102 221 interface - SWP deactivation while the UICC receives data 31g35.2.4.4.1 Test execution 31g35.2.4.4.2 Ini
18、tial conditions 31g35.2.4.4.3 Test procedure . 31g35.2.4.5 Test case 4: interaction with ETSI TS 102 221 interface - SWP deactivation while the UICC sends data 31g35.2.4.5.1 Test execution 31g35.2.4.5.2 Initial conditions 32g35.2.4.5.3 Test procedure . 32g35.2.4.6 Test case 5: interaction with ETSI
19、TS 102 221 interface - reset SWP while the UICC receives data 32g35.2.4.6.1 Test execution 32g35.2.4.6.2 Initial conditions 32g35.2.4.6.3 Test procedure . 32g35.2.4.7 Test case 6: interaction with ETSI TS 102 221 interface - reset SWP while the UICC sends data 33g35.2.4.7.1 Test execution 33g35.2.4.
20、7.2 Initial conditions 33g35.2.4.7.3 Test procedure . 33g35.2.4.8 Test case 7: interaction with ETSI TS 102 221 interface - activate SWP in ETSI TS 102 221 clock stop 33g35.2.4.8.1 Test execution 33g35.2.4.8.2 Initial conditions 33g35.2.4.8.3 Test procedure . 33g35.3 Physical characteristics . 34g35
21、.3.1 Temperature range for card operations . 34g35.3.1.1 Conformance requirements . 34g35.3.2 Contacts 34g35.3.2.1 Provision of contacts . 34g35.3.2.1.1 Conformance requirements 34g35.3.2.2 Contact activation and deactivation 34g35.3.2.2.1 Conformance requirements 34g35.3.2.3 Interface activation 34
22、g35.3.2.3.1 Conformance requirements 34g35.3.2.3.2 Test case 1: initial activation in low power mode . 35g35.3.2.3.3 Test case 2: initial activation in low power mode with corrupted frames . 36g35.3.2.3.4 Test case 3: no activation. 36g35.3.2.3.5 Void . 37g35.3.2.3.6 Test case 5: full power mode act
23、ivation 37g35.3.2.3.7 Test case 6: low power mode activation with re-transmission of ACT_SYNC. 37g35.3.2.3.8 Test case 7: full power mode activation with re-transmission of ACT_SYNC . 38g35.3.2.3.9 Void . 38g35.3.2.3.10 Test case 9: low power mode activation with multiple re-transmission of ACT_SYNC
24、 38g35.3.2.3.11 Test case 10: full power mode activation with re-transmission of ACT_READY 39g35.3.2.3.12 Test case 11: full power mode activation with multiple re-transmission of ACT_SYNC . 39g3ETSI ETSI TS 102 694-2 V10.3.0 (2015-03)5Release 105.3.2.3.13 Test case 12: subsequent activation in low
25、power mode . 40g35.3.2.3.14 Test case 13: subsequent activation in full power mode 40g35.3.2.3.15 Void . 41g35.3.2.4 Behaviour of a UICC in a terminal not supporting SWP 41g35.3.2.4.1 Conformance requirements 41g35.3.2.4.2 Test case 1: detect terminal not supporting SWP by TERMINAL CAPABILITIES, cla
26、sses B and C . 41g35.3.2.4.3 Test case 2: detect terminal not supporting SWP by TERMINAL CAPABILITIES, class A . 41g35.3.2.5 Behaviour of a terminal connected to a UICC not supporting SWP . 42g35.3.2.6 Inactive contacts 42g35.4 Electrical characteristics . 42g35.4.1 Operating conditions . 42g35.4.1.
27、1 Operating conditions . 42g35.4.1.2 Supply voltage classes. 42g35.4.1.2.1 Conformance requirements 42g35.4.1.2.2 Test case 1: ETSI TS 102 221 voltage classes B and C support 42g35.4.1.3 Vcc (C1) low power mode definition 43g35.4.1.3.1 Conformance requirements 43g35.4.1.3.2 Test case 1: operation in
28、 low power mode 43g35.4.1.4 Signal S1 . 43g35.4.1.4.1 Conformance requirements 43g35.4.1.4.2 Test case 1: S1 communication in voltage class B 44g35.4.1.4.3 Test case 2: S1 communication in voltage class C, full power mode 45g35.4.1.4.4 Test case 3: S1 communication in low power mode 46g35.4.1.5 Sign
29、al S2 . 47g35.4.1.5.1 Signal S2 47g35.4.1.5.2 Operating current for S2 47g35.5 Physical transmission layer 50g35.5.1 S1 Bit coding and sampling time 50g35.5.1.1 Conformance requirements . 50g35.5.1.2 Test case 1: communication with timing variation, default bit duration . 51g35.5.1.2.1 Test executio
30、n 51g35.5.1.2.2 Initial conditions 51g35.5.1.2.3 Test procedure . 51g35.5.1.3 Test case 2: communication with timing variation, extended bit duration 51g35.5.1.3.1 Test execution 51g35.5.1.3.2 Initial conditions 52g35.5.1.3.3 Test procedure . 52g35.5.1.4 Test case 3: S1 rise and fall time . 52g35.5.
31、1.4.1 Test execution 52g35.5.1.4.2 Initial conditions 52g35.5.1.4.3 Test procedure . 53g35.5.1.5 Test case 4: measurement of C6 input capacitance . 53g35.5.1.5.1 Test execution 53g35.5.1.5.2 Initial conditions 53g35.5.1.5.3 Test procedure . 53g35.5.1.5.4 Example for C6 input capacitance test impleme
32、ntation (informative) 53g35.5.1.6 Test case 5: communication with variation in bit duration . 54g35.5.1.6.1 Test execution 54g35.5.1.6.2 Initial conditions 54g35.5.1.6.3 Test procedure . 54g35.5.2 S2 switching management 54g35.5.2.1 Conformance requirements . 54g35.5.2.2 Test case 1: S2 switching ma
33、nagement . 54g35.5.2.2.1 Test execution 54g35.5.2.2.2 Initial conditions 54g35.5.2.2.3 Test procedure . 54g35.5.3 SWP interface states management 55g35.5.3.1 Conformance requirements . 55g35.5.3.2 Test case 1: SWP interface states management by the UICC . 55g35.5.3.2.1 Test execution 55g35.5.3.2.2 I
34、nitial conditions 55g3ETSI ETSI TS 102 694-2 V10.3.0 (2015-03)6Release 105.5.3.2.3 Test procedure . 55g35.5.3.3 Test case 2: UICC resume - P3 values and delay after transition sequence 55g35.5.3.3.1 Test execution 55g35.5.3.3.2 Initial conditions 55g35.5.3.3.3 Test procedure . 56g35.5.4 Power mode s
35、tates/transitions and Power saving mode 56g35.5.4.1 Conformance requirements . 56g35.5.4.2 Test case 1: power states in low power mode (ACT_POWER_MODE) 57g35.5.4.2.1 Test execution 57g35.5.4.2.2 Initial conditions 57g35.5.4.2.3 Test procedure . 57g35.5.4.3 Test case 2: power states in low power mode
36、 (non-ACT) 58g35.5.4.3.1 Test execution 58g35.5.4.3.2 Initial conditions 58g35.5.4.3.3 Test procedure . 58g35.5.4.4 Test case 3: power states in full power mode, without ETSI TS 102 221 . 58g35.5.4.4.1 Test execution 58g35.5.4.4.2 Initial conditions 58g35.5.4.4.3 Test procedure . 58g35.5.4.5 Test ca
37、se 4: power saving mode with ETSI TS 102 221 interface - restart ETSI TS 102 221 interface first . 58g35.5.4.5.1 Test execution 58g35.5.4.5.2 Initial conditions 59g35.5.4.5.3 Test procedure . 59g35.5.4.6 Test case 5: power saving mode with ETSI TS 102 221 interface - restart ETSI TS 102 613 interfac
38、e first . 59g35.5.4.6.1 Test execution 59g35.5.4.6.2 Initial conditions 60g35.5.4.6.3 Test procedure . 60g35.5.4.7 Test case 6: power saving mode with ETSI TS 102 600 interface - restart ETSI TS 102 600 interface first . 60g35.5.4.7.1 Test execution 60g35.5.4.7.2 Initial conditions 60g35.5.4.7.3 Tes
39、t procedure . 60g35.5.4.8 Test case 7: power saving mode with ETSI TS 102 600 interface - restart ETSI TS 102 613 interface first . 60g35.5.4.8.1 Test execution 60g35.5.4.8.2 Initial conditions 61g35.5.4.8.3 Test procedure . 61g35.5.4.9 Void. 61g35.5.4.10 Test case 9: power saving mode in SUSPENDED,
40、 with ETSI TS 102 221 interface restarted first . 61g35.5.4.10.1 Test execution 61g35.5.4.10.2 Initial conditions 61g35.5.4.10.3 Test procedure . 61g35.5.4.11 Test case 10: power saving mode in SUSPENDED, with ETSI TS 102 221 interface restarted after ETSI TS 102 613 interface . 62g35.5.4.11.1 Test
41、execution 62g35.5.4.11.2 Initial conditions 62g35.5.4.11.3 Test procedure . 62g35.6 Data link layer 62g35.6.1 Overview 62g35.6.2 Medium Access Control (MAC) layer 62g35.6.2.1 Bit order 62g35.6.2.1.1 Conformance requirements 62g35.6.2.1.2 Void . 63g35.6.2.2 Structure 63g35.6.2.2.1 Conformance require
42、ments 63g35.6.2.2.2 Test case 1: interpretation of incorrectly formed frames - ACT LLC . 63g35.6.2.2.3 Test case 2: interpretation of incorrectly formed frames - SHDLC RSET frames 63g35.6.2.2.4 Test case 3: interpretation of incorrectly formed frames - SHDLC I-frames 64g35.6.2.2.5 Test case 4: commu
43、nication with frames - idle bits and wakeup sequence . 64g35.6.2.3 Bit stuffing 65g3ETSI ETSI TS 102 694-2 V10.3.0 (2015-03)7Release 105.6.2.3.1 Conformance requirements 65g35.6.2.3.2 Test case 1: behaviour of UICC with bit stuffing in frame 65g35.6.2.4 Error detection . 66g35.6.2.4.1 Conformance re
44、quirements 66g35.6.2.4.2 Test case 1: RSET with CRC error 66g35.6.3 Supported LLC layers . 66g35.6.3.1 Supported LLC layers . 66g35.6.3.1.1 Conformance requirements 66g35.6.3.1.2 Test case 1: support of ACT LLC and ACT LPDU structure 66g35.6.3.1.3 Test case 2: support of SHDLC LLC and SHDLC LPDU str
45、ucture . 67g35.6.3.2 Interworking of the LLC layers . 67g35.6.3.2.1 Conformance requirements 67g35.6.3.2.2 Test case 1: error handling of ACT LLC on reception of corrupted frame, after SWIO activation . 68g35.6.3.2.3 Test case 2: ignore ACT LLC frame reception after the SHDLC link establishment . 68
46、g35.6.3.2.4 Test case 3: ignore ACT LLC frame reception in CLT session. 68g35.6.3.2.5 Test case 4: CLT session during SHDLC communication 69g35.6.3.2.6 Test case 5: closing condition of CLT session whereas SHDLC link has been established before CLT session 69g35.6.3.2.7 Test case 6: closing conditio
47、n of CLT session whereas SHDLC link has not been established before CLT session 70g35.6.3.2.8 Test case 7: interpretation of corrupted frames - single SHDLC frame 70g35.6.3.2.9 Void . 70g35.6.3.2.10 Test case 9: interpretation of corrupted frames - CLT frames . 70g35.6.3.2.11 Test case 10: first non
48、-ACT frame sent by CLF - initial interface activation 71g35.6.3.2.12 Test case 11: first non-ACT frame sent by CLF - subsequent interface activation . 71g35.6.4 ACT LLC definition . 72g35.6.4.1 ACT LLC definition 72g35.6.4.1.1 Conformance requirements 72g35.6.4.1.2 Test case 1: structure of ACT LPDU
49、 - full power mode . 72g35.6.4.1.3 Test case 2: structure of ACT LPDU - low power mode . 72g35.6.4.1.4 Test case 3: behaviour of UICC on reception of ACT frames - values of INF bit 73g35.6.4.1.5 Test case 4: RFU values in ACT_INFORMATION field . 73g35.6.4.1.6 Test case 5: extended bit durations as per ACT_INFORMATION field. 74g35.6.4.1.7 Test case 6: RFU values in ACT_INFORMATION field . 74g35.6.4.2 SYNC_ID verification process 75g35.6.4.2.1 Conformance requirements 75g35.7 SHDLC LLC definition 75g35.7.1 SHDLC overview . 75g35.7.1.1 Conformance requirements . 75g35.7.1.2 Test