1、 ENGINEERING MATERIAL SPECIFICATION Material Name Specification Number Date Action Changes 2014 06 11 N Status No replacement named L. Sinclair, NA 1996 10 23 Revised Added Para 3.4.6.5, 3.6.3, 3.6.5 R. Gordon 1995 08 01 Activated R. Gordon Page 1 of 16 PRINTED CIRCUIT BOARDS, MULTILAYER WSF-M22P2-A
2、1 NOT TO BE USED FOR NEW DESIGN 1. SCOPE This specification defines the performance requirements for rigid multilayer circuit boards (MLBs). A multilayer circuit board is defined as a circuit board with four or more layers. 2. APPLICATION This specification was released originally as the performance
3、 requirements for multilayer circuit boards to be used as the interconnect for electronic modules. 3. REQUIREMENTS 3.1 QUALITY SYSTEM REQUIREMENTS Material suppliers and part producers must conform to Quality System Requirements, QS-9000. Material specification requirements are to be used for initia
4、l qualification of materials. A Control Plan for ongoing production verification is required. This plan must be reviewed and approved by the relevant Ford Materials activity and/or Ford Supplier Technical Assistance (STA) prior to production parts submission. Appropriate statistical tools must be us
5、ed to analyze process/product data and assure consistent processing of the materials. Part producers using this material in their products, must use Ford approved materials and must conform to a process control plan which has been approved by STA and/or the relevant Materials Activity. 3.2 INFRARED
6、SPECTROPHOTOMETRY AND/OR THERMAL ANALYSIS Ford Motor Company, at its option, may conduct infrared and/or thermal analysis of material/parts supplied to this specification. The IR spectra and thermograms established for initial approval shall constitute the reference standard and shall be kept on fil
7、e at the designated material laboratory. All samples shall produce IR spectra and thermograms that correspond to the reference standard when tested under the same conditions. ENGINEERING MATERIAL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 2 of 16 3.3 CONDITIONING AND TEST CONDITIONS All test values i
8、ndicated herein are based on material conditioned in a controlled atmosphere of 23 +/- 2 C and 50 +/- 5 % relative humidity for not less than 24 h prior to testing and tested under the same conditions unless otherwise specified. 3.4 APPEARANCE Visually inspect the multilayer circuit board under a mi
9、nimum magnification of 1.75X for the following criteria. 3.4.1 Circuit Traces 3.4.1.1 Conductor Width Reduction from Design, max . Conductors greater or equal 20 % to 0.300 mm . Conductors less than 0.300 mm 0.075 mm 3.4.1.2 Cracks or voids are not permitted. Thickness reductions are allowable provi
10、ded they meet the minimum copper thickness requirements as designated on the engineering drawing. 3.4.1.3 Repair of broken traces is not permitted. 3.4.1.4 Rework of shorts between traces is permitted provided that reworked circuit meets the requirements in para 3.4.1.1. 3.4.2 Spacing Width The mini
11、mum width between noncommon conductors is 0.150 mm. Small specks or stray, nonelectrically connected, copper or other metallization are permitted provided that the specks are covered with soldermask that extends a minimum of 0.050 mm beyond the edge of each speck and a minimum of 0.100 mm spacing ex
12、ists to any circuit trace. 3.4.3 Laminate (IPC-A-600, Laminate Defect Guidelines) Appearance irregularities such as measling, crazing and weave exposure of the base laminate are allowable if they meet IPC-A-600, Class III requirements. Foreign material is allowable if it is at least 0.25 mm from a c
13、onductor. ENGINEERING MATERIAL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 3 of 16 3.4.4 Soldermask (IPC-SM-840, Class 3) . Cracked, peeled or delaminated soldermask is not permissible. . Missing soldermask is allowable provided that all conductors designed to be coated with soldermask are coated with
14、 soldermask and the soldermask extends a minimum of 0.050 mm into the adjacent space. . Voids are allowable provided that voids will not allow entrapment of flux. . Soldermask on solder pads is not allowable unless specified by the design. . Soldermask skips shall be acceptable provided that all con
15、ductors designed to be coated with soldermask are coated with solder mask and the soldermask extends a minimum of 0.050 mm into the space between two traces on at least one side of the space. 3.4.5 Component Diagram (Legend Silkscreen) . The component diagram must be legible from a distance of 25 cm
16、 to an observer with vision corrected to 20/20. . The component diagram ink is not permitted on solderable surfaces. 3.4.6 General 3.4.6.1 PTH Requirements Metallic nodules or other obstructions within a plated through hole are allowable provided that the internal diameter meets the minimum diameter
17、 as defined by the applicable drawing. Missing holes are not permitted. 3.4.6.2 NPTH Requirements Metallic nodules, plating, legend silkscreen ink, soldermask or other obstructions are not permitted in holes designated as non-plated through holes. Missing holes are not permitted. 3.4.6.3 Bond Enhanc
18、ement Treatment Color variations in the bond enhancement treatment are allowable. Localized areas of missing treatment are allowable provided that each location of missing treatment is less than 0.04 sq mm and the total area of missing treatment is less than 2 % of the metal area. ENGINEERING MATERI
19、AL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 4 of 16 3.4.6.4 Pink Ring Pink ring or missing bond enhancement treatment on the internal copper lands surrounding each plated through hole shall not extend more than 0.250 mm away from the hole wall to internal pad interfacer or 0.500 mm from hole wall o
20、n interlayer connections without internal pads. The maximum allowable conductor area affected by pink rink shall be less than 2 % of the total area per side. 3.4.6.5 Plugged Plated Through Holes All PTHs designated to be filled with plugging material shll befilled per the print. If not designated on
21、 the print, the minimum fill shall be a thickness which preents gas from passing through the PTH. A halo of solder is permissible around the hole circumference on side in which the hole was not plugged from. A continuous slug or film of solder over the entire plugged PTH is not permitted. 3.5 DIMENS
22、IONAL 3.5.1 Hole Size 3.5.1.1 Plated Through Holes (PTH) The diameter of one of each PTH hole size on each board on a panel shall be measured using pin gages or an alternative measuring instrument approved by Materials Engineering. 3.5.1.2 Non-plated Through Holes (NPTH) The diameter of each NPTH ho
23、le size on each board on a panel shall be measured using pin gages or an alternative measuring instrument approved by Materials Engineering. 3.5.2 Hole Location Measure the X and Y coordinates of 4 holes, one selected from each of the outer corners from each board on a panel. Hole locations shall be
24、 determined using an optical comparator. All measurements are to be determined to four decimal places with three place accuracy and be based on the datums defined on the applicable drawing. ENGINEERING MATERIAL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 5 of 16 3.5.3 External Registration Visually in
25、spect the MLB under a minimum magnification of 1.75X. 3.5.3.1 Copper Conductor to Hole Location 3.5.3.1.1 PTHs Accepting Leaded Components The minimum annular ring as a function of the nominal annular ring is defined in the table below. The minimum annular ring shall not be less than 0.050 mm regard
26、less of the nominal annular ring dimension. Nominal Annular Ring Minimum Annular Ring (mm) (mm) 0.300 0.150 3.5.3.1.2 PTHs Not Accepting Leaded Components (Vias) The minimum annular ring is 0.050 mm. 3.5.3.2 Soldermask to Copper Conductor Measure the true position location of the soldermask pattern
27、relative to the copper conductor pattern using an optical comparator. All measurements must be determined to four decimal places with three place accuracy. The maximum misregistration requirements for a screen printed and photoimageable soldermask are listed below. Soldermask Type (Diametrical True
28、Position) Screen Printed 0.280 mm Photoimaged 0.100 mm 3.5.3.3 Component Diagram (Legend Silkscreen) to Copper Conductor Measure the true position location of the component diagram pattern relative to the copper conductor pattern using an optical comparator conductor. All measurements must be determ
29、ined to four decimal places with three place accuracy. Diametrical True Position, max 0.280 mm ENGINEERING MATERIAL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 6 of 16 3.5.4 Internal Registration (IPC-TM-650, Method 2.1.1) Microsection a minimum of 3 plated through holes from each MLB on a manufacturi
30、ng panel per IPC-TM-650 Method 2.1.1. The holes selected should be representative of the smallest hole size of a particular design and a pad from each internal layer shall be represented in at least one of the holes evaluated. Evaluate each microsection under a minimum magnification of 100X. Each PT
31、H barrel shall be within its respective pad (No breakout is permitted) and the spacing between the PTH and a non-common conductor is 0.200 mm minimum. 3.5.5 Bow and Twist (IPC-TM-650, Method 2.4.22) 3.6 CONSTRUCTION 3.6.1 Surface Copper The thickness of each copper layer shall be measured using a mi
32、crosection per IPC-TM-650, Method 2.1.1. 3.6.2 Plated Through Hole Wall Thickness The plated through hole copper wall thickness shall be measured using a microsection per IPC-TM-650, Method 2.1.1. The average copper wall thickness must be greater than 0.025 mm. Localized reductions which do not redu
33、ce the copper hole wall thickness below 0.020 and do not reduce the average copper wall thickness below 0.025 mm are permissible. 3.6.3 Protective Coating The thickness of the protective coating, if applicable, covering unmasked copper areas shall be checked at three different locations on each DSB
34、for each manufacturing panel using microsectioning techniques per IPC-TM-650, Method 2.1.1, X-ray fluorescence or an alternative method approved by Materials Engineering. An average of 4 measurements from the center of each quadrant of a representative SMD (surface mount device) pad shall be reporte
35、d. The thickness measurements shall be taken such that the outer 0.025 mm wide periphery of each pad is excluded. Organic antioxidant treatments such as benzotriazole are exempt from this requirement. 3.6.4 Dielectric Thickness The thickness of the dielectric between each layer and the total thickne
36、ss shall be measured using a microsection per paragraph 3.5.4. The number of plies of glass, if applicable, shall be counted to insure compliance with the specific MLB print. ENGINEERING MATERIAL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 7 of 16 3.6.5 Hole Plugging Percent Fill When specified on the
37、 print, the percent fill of the hole plugging material shall be measured using a microsection per IPC-TM-650, Method 2.1.1 or an alternative method approved by Materials Engineering. The percent fill shall be defined as the thickness of the hole plugging material from the fill side to the bottom of
38、the meniscus on the opposite side divided by the length of the copper barrel multiplied by 100 % (See Figure 2). Voids in the plugging material are acceptable as long as they are not interconnected. H ole P lu g T h ick n essC op p er B a r r el L en g thP lu g g in g M a ter ia lFigure 2: Dielectri
39、c Plugged PTH/Via 3.7 ELECTRICAL All MLBs shall be tested for electrical continuity and isolation per the requirements of the particular design. 3.7.1 Electrical Continuity The resistance between any two common conductors shall have a resistance of less than 10 ohms. 3.7.2 Electrical Isolation The r
40、esistance between any two non-common conductors shall be at least 10 megaohms when tested with a voltage between 100 to 300 volts. ENGINEERING MATERIAL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 8 of 16 3.8 GENERAL 3.8.1 Cleanliness, max 1.5 ug NaCl/sq cm (IPC-TM-650, Method 2.3.26) The ionic cleanli
41、ness shall be measured before and after the application of soldermask using an Ionograph or method approved by Materials Engineering. Table 1 provides the maximum ionic cleanliness levels for common alternative ionic cleanliness measurement techniques. Table 1 - Ionic Cleanliness Contamination Level
42、s Method ug NaCl/cm2 Omega Meter 1.05 Ion Chaser 2.40 3.8.2 Solderability (WSF-M22P1-A1) Class will be defined on the specific MLB print. If no class is specified, class 1 is assumed. 3.8.3 Plated Through Hole Integrity 3.8.3.1 As Manufactured (Prior to Thermal Stress) Microsection PTHs per paragrap
43、h 3.5.4 and evaluate under a minimum of 100X magnification for the following requirements: . Plating voids are not allowed. . Burrs, nodules and glass fiber protrusions are allowed provided the minimum hole diameter is met. . Interplane (internal copper pads) to through hole plating separation or ev
44、idence of residues in the interface between the interplane and through hole copper are not permitted. . Laminate voids greater than 0.075 mm in dimension are not allowed. . Negative etchback of the copper interlayers shall not exceed 0.0125 mm. . Lifted external pads are not allowed. ENGINEERING MAT
45、ERIAL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 9 of 16 3.8.3.2 After Thermal Stress (Solder Float) Thermally stress a PTH coupon removed from a production representative circuit board per IPC-TM-650, method 2.6.8 with the following exceptions: . 4 h conditioning at standard conditions prior to ther
46、mal stress. (See paragraph 3.3) . Test coupons shall not be baked prior to testing. . Solder bath temperature shall be 235 C. After thermal stress exposure, microsection PTHs per paragraph 3.5.4 and evaluate under a minimum of 100X magnification for the following requirements: . Plating voids are no
47、t allowed. . Innerplane (internal copper pads) to through hole plating separation or evidence of residues in the interface between the innerplane and through hole copper are not permitted. Residues between the external copper foil and the through hole plating are permitted provided that the residue
48、does not extend into the through hole plating and corner cracking is not exhibited. . Separation of plating is not permitted. . Cracks in the PTH hole wall, internal copper pads or external copper pads are not permitted. . Laminate voids greater than 0.075 mm in dimension are not permitted. . Lifted
49、 external pads are allowed provided that 50 % of the pad annular ring width remains bonded to the base laminate. . Resin recession or hole wall pullaway is permitted provided the resin recession is no greater than 0.075 mm as measured from the plated through hole copper and the resin recession does not extend more than 5 percent of the cumulative hole wall length. ENGINEERING MATERIAL SPECIFICATION WSF-M22P2-A1 WP 3948-b Page 10 of 16 3.9 DURABILITY 3.9.1 Resistance to Solvents, weight gain, max 2 % (IPC-TM-650, method 2.3.3) No damage or degradat
