1、INTERNATIONAL TELECOMMUNICATION UNIONCCITT V.17THE INTERNATIONALTELEGRAPH AND TELEPHONECONSULTATIVE COMMITTEEDATA COMMUNICATIONOVER THE TELEPHONE NETWORKA 2-WIRE MODEM FOR FACSIMILEAPPLICATIONS WITH RATES UPTO 14 400 bit/sRecommendation V.17Geneva, 1991FOREWORDThe CCITT (the International Telegraph
2、and Telephone Consultative Committee) is a permanent organ of theInternational Telecommunication Union (ITU). CCITT is responsible for studying technical, operating and tariffquestions and issuing Recommendations on them with a view to standardizing telecommunications on a worldwidebasis.The Plenary
3、 Assembly of CCITT which meets every four years, establishes the topics for study and approvesRecommendations prepared by its Study Groups. The approval of Recommendations by the members of CCITT betweenPlenary Assemblies is covered by the procedure laid down in CCITT Resolution No. 2 (Melbourne, 19
4、88).Recommendation V.17 was prepared by Study Group XVII and was approved under the Resolution No. 2procedure on the 22 of February 1991._CCITT NOTEIn this Recommendation, the expression “Administration” is used for conciseness to indicate both atelecommunication Administration and a recognized priv
5、ate operating agency. ITU 1991All rights reserved. No part of this publication may 0 be reproduced or utilized in any form or by any means, electronicor mechanical, including photocopying and microfilm, without permission in writing from the ITU.Recommendation V.17 1Recommendation V.17Recommendation
6、 V.17A 2 -WIRE MODEM FOR FACSIMILE APPLICATIONS WITHRATES UP TO 14 400 bit/s1 IntroductionThis Recommendation defines the modulation methods and operating sequences for a modem intended onlyfor use in high speed facsimile applications.Appropriate T-Series Recommendations should be consulted regardin
7、g operating procedures and otherfeatures employed in facsimile transmission applications, as these differ from those recommended for high speedmodems for general applications.The modem has the following principal characteristics:a) Provision for half duplex operation at data signalling rates of: 14
8、400 bit/s synchronous, 12 000 bit/s synchronous, 9600 bit/s synchronous, 7200 bit/s synchronous;b) Quadrature amplitude modulation with synchronous line transmission at 2400 symbols per second.c) Inclusion of data scramblers, adaptive equalizers and eight-state trellis coding.d) Two sequences for tr
9、aining and synchronization: long train and resync.2 Line signals2.1 Carrier frequencyThe channel carrier frequency is 1800 1 Hz. The receiver must be able to operate with received frequencyoffsets of up to 7 Hz.2.2 ModulationThe modulation rate shall be 2400 0.01% symbols per second.2.3 Signal eleme
10、nt codings2.3.1 Signal element codings for 14 400 bit/sThe scrambled data stream to be transmitted is divided into groups of six consecutive data bits, which areordered according to their time of occurrence. As shown in Figure 1/V.17, the first two bits in each group, Q1nand Q2n(where n designates t
11、he sequence number of the group) are first differentially encoded into Y1nand Y2naccording toTable 1/V.17.2 Recommendation V.17T T T+TTQ1nnnnnnQ6Q5Q4Q3Q2nY1nnnnnQ6Q5Q4Q3Y2nY0abS1abS2000000000a b S1 S21111111+T1701600-92/d01nnY1Y2n-1Y2Y1n-1SignalelementmappingSeeFigures2/V.17 to5/V.17Convolutional en
12、coderDifferential encoderSeeTable1/V.17FIGURE 1/V.17Trellis coding at 14 400, 12 000, 9600 and 7200 signalling ratesTABLE 1/V.17Differential coding for use with trellis codingInput Previous outputs OutputsQ1nQ2nY1n1Y2n1Y1nY2n000000001111111100001111000011110011001100110011010101010101010100110011110
13、011000101101001101001Recommendation V.17 3The two differentially encoded bits Y1nand Y2nare used as inputs to a systematic convolutional encoderwhich generates a redundant bit Y0n. This redundant bit and the six information-carrying bits Y1n, Y2n, Q3n, Q4n, Q5nand Q6nare then mapped into the coordin
14、ates of the signal element to be transmitted according to the signal spacediagram shown in Figure 2/V.17.0111100 0110010 0011100 1110010 00011000111001 0100101 0011001 1000101 00010010111011 0110111 1111011 11101110111000 0111110 0101000 1111110 10010000110001 0101101 0010001 10011010110100 0100010
15、0010100 1100010 00001000011011 0100111 1011011 11001111111000 0011110 1101000 10111101110001 1101101 10100011110100 1000010 10101000001011 10001110110000 0101110 0100000 1101110 10000000101011 0010111 1101011 10101111111100 0010010 1011100 10100101111001 1100101 10110011110000 1001110 11000001001011
16、 00001111001100 1111010 0101100 01110100000101 1001001 0010101 0101001 01101011110011 1111111 01100110001000 1110110 0011000 01101100001101 1000001 0011101 01000011000100 1101010 0100100 01010101010011 1101111 00100111010110 1011000 00101101011101 11000011100100 100101000000110000000 1100110 0010000
17、 01001101100011 1011111 0100011 00111111011010 1101100 00110101010101 1101001 11101011010000 10001101000011 0001111011111101111010101111111110110011112 4 6 8 8428627000000100001010A 6 4 2180 2 4 6 8BC0000110 0001110090D0000001T1701610-92/d02FIGURE 2/V.17A 128-point signal structure used with the tre
18、llis-coded 14 400 bit/s data signalling rateNote The binary numbers denote Q6 , Q5 , Q4 , Q3 , Y2 , Y1 , Y0 . A, B, C and D refer to synchronizing signal elements.nnnnnnn4 Recommendation V.172.3.2 Signal element codings for 12 000 bit/sThe scrambled data stream to be transmitted is divided into grou
19、ps of five consecutive data bits, which areordered according to their time of occurrence. As shown in Figure 1/V.17, the first two bits in each group, Q1nand Q2n(where n designates the sequence number of the group) are first differentially encoded into Y1nand Y2naccording toTable 1/V.17.The two diff
20、erentially encoded bits Y1nand Y2nare used as inputs to a systematic convolutional encoderwhich generates a redundant bit Y0n. This redundant bit and the five information-carrying bits Y1n, Y2n, Q3n, Q4nand Q5nare then mapped into the coordinates of the signal element to be transmitted according to
21、the signal spacediagram shown in Figure 3/V.17.101011270A 2180BC090D101100001010101001000101100110000000011111011011000100100010000001101101001110101000101111 6 4 2 2 4 6 4 6642101110 001111 111100 111001011110 100111 001100 001001100101 100000 110011 010010110101 110000 111011 000010011100 011001 1
22、10110 010111010100 010001 111110 000111001101 001000 100011 011010111101 111000 101010001011000110 111111 110100 110001010110 110111 100100 100001000011 111010 010101 010000010011 110010 011101 011000T1701620-92/d03FIGURE 3/V.17A 64-point signal structure used with the trellis-coded 12 000 bit/sdata
23、 signalling rateNote The binary numbers denote Q5 , Q4 , Q3 , Y2 , Y1 , Y0 . A, B, C and D refer to synchronizing signal elements.nn nnnnRecommendation V.17 52.3.3 Signal element codings for 9600 bit/sThe scrambled data stream to be transmitted is divided into groups of four consecutive data bits, w
24、hich areordered according to their time of occurrence. As shown in Figure 1/V.17, the first two bits in each group, Q1nand Q2n(where n designates the sequence number of the group) are first differentially encoded into Y1nand Y2naccording toTable 1/V.17.The two differentially encoded bits Y1nand Y2na
25、re used as inputs to a systematic convolutional encoderwhich generates a redundant bit Y0n. This redundant bit and the four information-carrying bits Y1n, Y2n, Q3nand Q4nare then mapped into the coordinates of the signal element to be transmitted, according to the signal space diagramshown in Figure
26、 4/V.17.01100 11010 0010010001 0110101011 1011101000 10110 1100011001 0010110100 010100001110000 0011011100 10010111011001100000 1111001001000100111110101111114 884270A 8 4180 48BC090D00001011101101100111T1701630-92/d04FIGURE 4/V.17A 32-point signal structure for trellis-coded 9600 bit/sdata signall
27、ing rateNote The binary numbers denote Q4 , Q3 , Y2 , Y1 , Y0 . A, B, C and D referto synchronizing signal elements.nnnnn2.3.4 Signal element codings for 7200 bit/sThe scrambled data stream to be transmitted is divided into groups of three consecutive data bits, which areordered according to their t
28、ime of occurrence. As shown in Figure 1/V.17, the first two bits in each group, Q1nand Q2n(where n designates the sequence number of the group) are first differentially encoded into Y1nand Y2naccording toTable 1/V.17.6 Recommendation V.17The two differentially encoded bits Y1nand Y2nare used as inpu
29、ts to a systematic convolutional encoderwhich generates a redundant bit Y0n. This redundant bit and the three information-carrying bits Y1n, Y2nand Q3narethen mapped into the coordinates of the signal element to be transmitted according to the signal space diagram shown inFigure 5/V.17.1011270A 2180
30、BC090D1100001010011101011010001111 6 2 2 6 6621110 01110100 00010101 000010100011T1701640-92/d05FIGURE 5/V.17A 16-point signal structure for trellis-coded 7200 bit/sdata signalling rateNote The binary numbers denote Q3 , Y2 , Y1 , Y0 . A, B, C and D referto synchronizing signal elements.nnnn2.4 Tran
31、smitted spectraWith continuous binary ONEs applied to the input of the scrambler, the transmitted energy density at 600 Hzand 3000 Hz should be attenuated by 4.5 2.5 dB with respect to the maximum energy density between 600 Hz and3000 Hz.3 Interchange circuits3.1 List of interchange circuitsReferenc
32、es in the Recommendation to V.24 interchange circuit numbers are intended to refer to the functionalequivalent of such circuits and are not intended to imply the physical implementation of such circuits. For example,references to circuit 103 should be understood to refer to the functional equivalent
33、 of circuit 103 (see Table 2/V.17).Recommendation V.17 7TABLE 2/V.17Interchange circuitsNumber Description102103104105106107108/1 or108/2109114115125Signal ground or common returnTransmitted dataReceived dataRequest to sendReady for sendingData set readyConnect data set to line (Note)Data terminal r
34、eady (Note)Data channel received line signal detectorTransmitter signal element timing (DCE source)Receiver signal element timing (DCE source)Calling indicatorNote This circuit shall be capable of operating as circuit 108/1 or circuit 108/2.3.2 Transmit dataThe modem shall accept data from the facsi
35、mile control function on circuit 103; the data on circuit 103 shall beunder the control of circuit 114.3.3 Receive dataThe modem shall pass data to the facsimile control function on circuit 104; data on circuit 104 shall be underthe control of circuit 115.3.4 Timing arrangementsClocks shall be inclu
36、ded in the modem to provide the facsimile control function with transmitter elementtiming on circuit 114 and receiver signal element timing on circuit 115.3.5 Data rate controlThis shall be provided by a connection between the modem and the facsimile control function; the nature ofthis connection is
37、 beyond the scope of this Recommendation.3.6 Circuits 106 and 109 response timesAfter the training and synchronizing sequences defined in 5, circuit 106 shall follow OFF to ON or ON toOFF transitions of circuit 105 within 3.5 ms. The OFF to ON transition of circuit 109 is part of the training sequen
38、cespecified in 5. Circuit 109 shall turn OFF 30 to 50 ms after the level of the received signal appearing at the lineterminal of the modem falls below the relevant threshold defined in 3.7. Following a dropout, after the initialhandshake, circuit 109 shall turn ON 40 to 205 ms after the level of the
39、 received signal appearing at the line terminal ofthe modem exceeds the relevant threshold defined in 3.7.3.7 Circuit 109 threshold 43 dBm ON. 48 dBm OFF.8 Recommendation V.17The condition of circuit 109 between the ON and OFF levels is not specified except that the signal detectorshall exhibit a hy
40、steresis action, such that the level at which the OFF to ON transition occurs shall be at least 2 dBgreater than that for the ON to OFF transition.Circuit 109 thresholds are specified at the input to the modem when receiving scrambled binary ONEs.Administrations are permitted to change these thresho
41、lds where transmission conditions are known.Note Circuit 109 ON to OFF response time should be suitably chosen within the specified limits to ensurethat all valid data bits have appeared on circuit 104.3.8 ClampingThe DCE shall hold, where implemented, circuit 104 in the binary ONE condition and cir
42、cuit 109 in the OFFcondition when circuit 105 is in the ON condition and, where required to protect circuit 104 from false signals, for aperiod of 150 25 ms following the ON to OFF transition on circuit 105. The use of this additional delay is optional,based on system considerations.4 Scrambler and
43、descramblerThe modem shall use a self-synchronizing scrambler/descrambler with the generator polynomial:1 + x18+ x23At the transmitter, the scrambler shall effectively divide the message data sequence by the generatingpolynomial. The coefficients of the quotient of this division, taken in descending
44、 order, form the data sequence whichshall appear at the output of the scrambler. At the receiver, the received data sequence shall be multiplied by thescrambler generating polynomial to recover the message sequence.5 Operating sequences5.1 Training and synchronizing sequencesTwo separate sequences o
45、f training and synchronizing signals are defined in Table 3/V.17.The long train sequence is for initial establishment of a connection or for retraining when needed.The resync. sequence is for resynchronization after a successful long train.TABLE 3/V.17Training and synchronizing signalsSegment 1 Segm
46、ent 2 Segment 3 Segment 4ABABalternationsEqualizer trainingsignalBridgesignalScrambledONEsTotal symbolintervalApproximatetime (ms)Long train 256 2976 64 48 33441393Resync. 256 2938 64 48 33421142Recommendation V.17 95.1.1 Segment 1: ABAB alternationsThis segment consists of alternations between stat
47、es A and B as shown in Figures 2/V.17 to 5/V.17.5.1.2 Segment 2: equalizer training signalThis segment consists of the sequential transmission of four signal elements A, B, C, and D as shown inFigures 2/V.17 to 5/V.17.The equalizer conditioning pattern is a pseudo-random sequence at 4800 bit/s gener
48、ated by the1 + x18+ x23data scrambler. During segment 2, any differential quadrant encoding is disabled and the scrambled dibitsare encoded as shown in Table 4/V.17.With a binary ONE applied to the input, the initial scrambler state shall be selected to produce the followingscrambler output pattern
49、and corresponding signal elements:TABLE 4/V.17Encoding for four phase training signal00C01D00C01D00C01D00C01D00C01D00C01D10B01D10B01DSegment 2Dibit Signal state00011110CDAB5.1.3 Segment 3: bridge signalThis segment, which is used only during an initial long train, consists of a 16-bit binary sequence transmittedeight times. The sequence as defined in Table 5/V.17 is scrambled, and transmitted at 4800 bit/s using the signalelements A, B, C, and D as defined in Figures 2/V.17 to 5/V.17.10 Re
