1、INTERNATIONAL TELECOMMUNICATION UNION)45G134 8 TELECOMMUNICATIONSTANDARDIZATION SECTOROF ITU05“,)#G0G0$!4!G0G0.%47/2+3).4%2(b) that Recommendation X.21 defines the interface between a Data Terminal Equipment (DTE) and DataCircuit-terminating Equipment (DCE) for synchronous operation on public data n
2、etworks;(c) that it is desirable for characteristics of the interface carrying a multiplexed bit stream between a DTEand a multiplex DCE of a public data network to be standardized;unanimously declaresthat the interface between the DTE and the DCE in a public data network using a multiplexed channel
3、configuration employing synchronous transmission should be as defined in this Recommendation.1 Scope1.1 This Recommendation defines the interface between a DTE and a multiplex DCE, operating at 48 000 bit/sand multiplexing a number of Recommendation X.21 subscriber channels employing synchronous tra
4、nsmission.1.2 The number of Recommendation X.21 subscriber channels is limited by the number of subscriber channelsallowed in the network multiplex structure (see 4).1.3 The provision of all services supported by Recommendation X.21 is possible.2 DTE/DCE physical interface elements (see Table 1/X.22
5、)2.1 Electrical characteristicsThe electrical characteristics of the interchange circuits at both the DCE side and the DTE side of the interfacewill comply with Recommendation X.27 with implementation of the cable termination in the load.2.2 Mechanical characteristicsRefer to ISO 4903 (15-pole DTE/D
6、CE interface connector and contact number assignments) for mechanicalarrangements.2.3 Functional characteristics of the interchange circuitsDefinitions of the interchange circuits G, T, R, C, I, S and F are given in Recommendation X.24 and in 4below.2 Fascicle VIII.2 - Rec. X.22TABLE 1/X.22Interchan
7、ge Directioncircuit Nameto DCE from DCE RemarkGTRCISFSignal ground or common returnTransmitReceiveControlIndicationSignal element timingFrame start identificationXXXXXXSee NoteNote - This conductor may be used to reduce environmental signal interference at the interference. In the case of shieldedin
8、terconnecting cable, the additional connection considerations are part of Recommendation X.24 and ISO 4903.2.4 Call control and failure detection proceduresCall control and failure detection procedures shall operate as specified in Recommendation X.21 on eachsubscriber channel independent of other s
9、ubscriber channels.2.4.1 Quiescent statesThe quiescent states shall be in accordance with Recommendation X.21, 2.5.2.4.2 Failure detectionSee Recommendation X.27, 9 for association of the receiver circuit failure detection types.2.4.2.1 Fault conditions on interchange circuitsThe DTE should interpre
10、t a fault condition on circuit R as r = 0 on all channels using failure detection type 2,a fault condition on circuit I as i = OFF on all channels using failure detection type 1, and a fault condition on bothcircuits R and I as r = 0, i = OFF (DCE not ready) on all channels.Alternatively a fault con
11、dition on one of these circuits, R or I, may be interpreted by the DTE as r = 0, i = OFF(DCE not ready), using failure detection type 3.The DCE will interpret a fault condition on circuit T as t = 0 on all channels using failure detection type 2, afault condition on circuit C as c = OFF on all chann
12、els using failure detection type 1, and a fault condition on bothcircuits T and C as t = 0, c = OFF on all channels (DTE uncontrolled not ready).Alternatively, a fault condition on one of these circuits, T or C, may be interpreted by the DCE as t = 0,c = OFF (DTE uncontrolled not ready), using failu
13、re detection type 3.2.4.2.2 DCE fault conditionIndication of the DCE failure condition shall be in accordance with Recommendation X.21, 2.6.2.A DCE failure condition may effect all subscriber channels at the DTE/DCE interface.2.4.2.3 Signal element timing provisionThe provision of signal element tim
14、ing shall be in accordance with Recommendation X.21, 2.6.3.Fascicle VIII.2 - Rec. X.22 32.4.3 Elements of the call control phaseThe elements of the call control phase, for each channel, shall be in accordance with Recommendation X.21, 4 with the exception that byte timing is not used.2.4.4 Data tran
15、sfer phaseThe data transfer phase, for each channel, shall be in accordance with Recommendation X.21, 5.2.4.5 Clearing phaseThe clearing phase, for each channel, shall be in accordance with Recommendation X.21, 6.3 Alignment of call control characters and error checking3.1 Character alignmentFor the
16、 interchange of information between the DTE and the DCE for call control purposes, it is necessary toestablish correct alignment of characters. Each sequence of call control characters to and from the DCE shall bepreceded by two or more contiguous 1/6 (“SYN“) characters.3.1.1 Certain Administrations
17、 will require the DTE to align call control characters transmitted from the DTE toeither SYN characters delivered to the DTE or to the signals on the frame start identification interchange circuit (F).3.1.2 Certain Administrations will permit call control characters to be transmitted from the DTE in
18、dependently ofthe SYN characters delivered to the DTE.3.2 Error checkingOdd parity according to Recommendation X.4 applies for the interchange of IA5 characters for call controlpurposes.4 Multiplex structureDepending on the multiplex structure used by the network, the structure of the multiplexed bi
19、t stream will beone of two different types.4.1 Multiplex structure in networks providing 6 bit-bytesThe DCE shall deliver to and receive from the DTE a 6-bit byte interleaved multiplexed bit stream containinga number of subscriber channels. The allocation of the subscriber channels should be:5 chann
20、els (phases) of 9600 bit/s or10 channels of 4800 bit/s or20 channels of 2400 bit/s or80 channels of 600 bit/s oran appropriate mix of channel data signalling rates having an aggregate bit rate of 48 kbit/s.The multiplex structure is divided into five phases of 9600 bit/s, where each phase shall be h
21、omogeneous withregard to the subscriber data signalling rates.4.1.1 Interchange circuits and interface signalling schemeThe interchange circuits between the DTE and the DCE are shown in Figure 1/X.22 and a timing diagram forthe signals is given in Figure 2/X.22.The signalling over the interchange ci
22、rcuits is as follows.4 Fascicle VIII.2 - Rec. X.22The transmit (T) and receive (R) circuits will convey in one time slot six consecutive user data bits for onesubscriber channel (see Figure 2/X.22).The control (C) and indication (I) circuits will convey the appropriate signal levels in accordance wi
23、thRecommendation X.21 for the data channel which in the same time slot have bits conveyed over the respective datacircuits.Change of condition on circuit C shall take place at the OFF to ON transition of circuit S at the beginning ofthe first bit in the 6-bit byte. The condition on circuit C shall b
24、e steady for the whole 6-bit byte.Change of condition on circuit I will take place at the OFF to ON transition of circuit S at the beginning of thefirst bit in the 6-bit byte and the condition will be steady for the whole 6-bit byte.The signal element timing (S) will operate for continuous isochrono
25、us transmission at 48 kbit/s.The frame start identification circuit (F) will indicate the frame start with an OFF condition appearing in thelast bit of each frame. For networks using Recommendation X.50 division 2 multiplexing, the frame length will be480 bits. For networks using Recommendation X.50
26、 division 3 multiplexing in which the user rate of 600 bit/s is notincluded, the frame length will be 120 bits.4.2 Multiplex structure in networks providing 8-bit bytesThe DCE shall deliver to and receive from the DTE an 8-bit byte interleaved multiplexed bit stream containinga number of subscriber
27、channels. The allocation of the subscriber channels should be:5 channels (phases) of 9600 bit/s or10 channels of 4800 bit/s or20 channels of 2400 bit/s or80 channels of 600 bit/s oran appropriate mix of channel data signalling rates having an aggregate bit rate of 48 kbit/s.The multiplex bit stream
28、is divided into five phases of 9600 bit/s, where each phase shall be homogeneouswith regard to the subscriber data signalling rates.4.2.1 Interchange circuits and interface signalling schemeThe interchange circuits between the DTE and DCE are shown in Figure 1/X.22 and a timing diagram for thesignal
29、s is given in Figure 3/X.22. The signalling over the interchange circuits is as follows.The transmit (T) and receive (R) circuits will convey in one time slot eight consecutive user data bits for onesubscriber channel (see Figure 3/X.22).The control (C) and indication (I) circuits will convey the ap
30、propriate signal levels in accordance withRecommendation X.21 for the data channel which in the same time slot have bits conveyed over the respective datacircuits.Change of condition on circuit C shall take place at the OFF to ON transition of circuit S at the beginning ofthe first bit in the 8-bit
31、byte. The condition on circuit C shall be steady for the whole 8-bit byte.Change of condition on circuit I will take place at the OFF to ON transition of circuit S at the beginning of thefirst bit in the 8-bit byte and the condition will be steady for the whole 8-bit byte.The signal element timing (
32、S) will operate for continuous isochronous transmission at 48 kbit/s.The frame start identification circuit (F) will indicate the frame start with an OFF condition appearing in theposition of the last bit of each 640-bit frame. As an optional facility each frame start could be followed by a code whichwill indicate the actual channel allocation. This facility is for further study.Fascicle VIII.2 - Rec. X.22 55 Test loopsEstablishment of test loops for DTE tests and network maintenance is for further study.6 Fascicle VIII.2 - Rec. X.22
