1、EIA JEPL26 9b 3234800 0571737 741 i EINJEDEC PUBLICATION Guideline for Developing and Documenting Package Electrical Models Derived from Computational Analysis EIAfJEP126 MAY 1996 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT NOTICE EWJEDEC Standards and Publications contain material that
2、 has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. EIAJEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and pu
3、rchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturin
4、g or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally. EIA/JEDEC Standards and Publications are adopted without regard t
5、o whether their adoption may involve patents or articles, materials, or processes. By such action, EWJEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJEDEC Standards or Publications. The information included in EWJEDEC Stan
6、dards and Publications represents a sound approach to product specification and application, principally fi-om the solid state device manufacturer viewpoint. Within the EIA/JEDEC organization there are procedures whereby an EWJEDEC Standard or Publication may be further processed and ultimately beco
7、mes an ANSEIA Standard. Inquiries, comments, and suggestions relative to the content of this EWJEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2500 Wilson Boulevard, Arlington, VA 22201. Published by OELECTRONIC INDUSTRIES ASSOCIATION 1996 Engi
8、neering Department 2500 Wilson Boulevard Arlington, VA 22201 “Copyright“ does not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of the JEDEC Publication 2 1 “Manual of Organization and Procedure“. PRICE: Please refer to the current
9、 Catalog of EIA, JEDEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights reserved EIMJEDEC Publication No. 126 GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MOD
10、ELS DERIVED FROM COMPUTATIONAL ANALYSIS 1 Scope 2 Introduction 3 Model inputs 3.1 Stimulus conditions 3.1.1 Rise time 3.1.2 Signal waveform 3.1.3 Frequency range 3.2 Package description 3.3 Environment description 3.3.1 Application specific environment 3.3.2 Standard model environment 4 Model output
11、 parameters Page 1 1 5 Model documentation -1- EIA JEPL26 96 3234600 0573740 236 W EINJEDEC Publication No. 126 This page intentionally left blank -11- EIA JER126 96 3234600 0571741 172 EINJEDEC Publication No. 126 Page 1 GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FRO
12、M COMPUTATIONAL ANALYSIS (From JEDEC Council Ballot JCB-95-39, formulated under the cognizance of JC-15.2 Subcommittee on Electrical Phenomena in Electronic Packaging.) 1 Scope This guideline provides a methodology for the creation, use and documentation of IC package nominal electrical models using
13、 computational techniques. Several environmental parameters and boundary conditions need specification before a package model can be created; these parameters must be consistent with the chosen simulation and measurement techniques. Verification of model accuracy is essential but beyond the scope of
14、 this document. In addition, recommendations are made for a standard model environment when relative (not absolute) comparisons of package performance are desired. 2 Introduction A package electrical model) can be created fi-om the results of an electromagnetic analysis of the package geometry and m
15、aterial properties. The output of this analysis is a representation of the package that approximates its electrical behavior. An electrical model must account for the environment in which the package resides. Assumptions regarding the interconnect near the package need consideration; such as the cha
16、racteristics of the circuit board (i.e., dielectric thickness, presence of ground planes, etc.) to which the package is attached. Process variations wili influence the package electrical parasitics but this guideline will only address nominal dimensions, material properties and resultant model. The
17、final model format depends upon the simulation technique by which the model will be evaluated. For example, time domain simulation in SPICE typically employs a lumped element model of the package, while a frequency domain simulation will often use an S-parameter model. Stimulus conditions will also
18、affect the form of the package model; for instance, a very short risetime input pulse might make it necessary to account for frequency dependent material properties to accurately represent the package over a broad range of fiequency. 1) A package model is the circuit representation of the package; t
19、ypically generated using electromagnetic field analysis software. This model is usually incorporated into a higher level simulation tool, such as SPICE that can predict overall circuit performance. EIA JEPlFb 96 3234600 0573742 O09 EINJEDEC Publication No. 126 Page 2 3 Model inputs 3.1 Stimulus cond
20、itions 3.1.1 Rise time Signal risetime describes, in general terms, the time that it takes a time domain signal to rise or fall between two threshold limits. This parameter is often called out when time domain simulators such as SPICE will be used, but the specifics of the drivers are not well defin
21、ed. Short rise times may indicate that frequency dependencies such as skin effect and dielectric loss should be considered. 3.1.2 Signal waveform The description of the time domain input waveform not only captures the rise time, described above, but also defines the spectral content of the signal th
22、at passes through the package. Specification of the signal waveform usually occurs when the device drivers are well defined. 3.1.3 Frequency range The range of analog frequencies over which a package model must be stimulated. 3.2 Package Description The package nominal material properties and geomet
23、ries must be clearly defined prior to the electromagnetic analysis and should be detailed in the final report. A partial list of these properties is included below; any other properties assumed in creating the package model must also be described. Package Geometry - Line width(s) - Line thickness(es
24、) - Line pitch(es) - Dielectric dimension - Pin dimensions - Via dimensions - Any other geometry assumptions Material Properties - Material type(s) - Dielectric constant, loss tangent - Conductivity - Permeability EIA JEPL26 96 LI 323IihOCl 0573743 T45 EINJEDEC Publication No. 126 Page 3 3.3 Environ
25、ment description 3.3.1 Application specific environment The package environment must be specified; including any relevant socket, circuit board and enclosure information. The following material properties and dimensions must be considered: Board Geometry - Line width(s) - Line thicknesstes) - Line p
26、itch(es) - Via diameterts) - Dielectric thicknesstes) - Ground plane Material properties - Material types - Dielectric constants, loss tangents - Conductivities In some instances the model environment may also include a socket or a probe (typically used in measurement verification). Any other struct
27、ures that may influence the electromagnetic behavior of the package should be fully described. For example, a package enclosed in a PCMCIA card may behave differently than the same package mounted on a card inside a mainfiame computer card cage. 3.3.2 Standard model environment A standard environmen
28、t is suggested for use in creating a package model when the final use conditions are unknown. When applied consistently, these conditions will provide a comparison of relative package performance. The resulting model will not necessarily be valid for specific applications and should be carefully exa
29、mined prior to use in predicting actual package performance. Typically a package is mounted to a printed circuit board. The standard surface mount board is defined as follows: Geometry: Line thickness = 1 oz copper Ground plane = nonmagnetic Ground plane position = O or 0.152 or 1.588 mm from bottom
30、 of external package pins. Ail signals routed to package on top of dielectric EINJEDEC Publication No. 126 Page 4 Material Properties: Dielectric material = FR4 Dielectric constant = 4.3 Typ. Conductor material = copper Conductivity = 5.7 * 10E+7 SM 4 Model output parameters Package models can be pr
31、esented in a variety of ways. The circuit representation of the package should be defined before the electromagnetic analysis is performed. Some, but not all, possible representations are listed below: - Inductance matrix - Capacitance matrix - Resistance matrix - Impedance matrix - S-Parameters - L
32、umped element (inductance, capacitance, resistance) equivalent circuit - Mixed lumped / transmission line equivalent circuit 5 Model documentation A fully documented package model should include the following information: INPUT - Material properties -Packagegeomet - - Environment geometry - Stimulus
33、 conditions (rise time, or waveform, or frequency range) ELECTROMAGNETIC ANALYSIS TECHNIQUES - Model algorithm - Algorithm limitations EQUIVALENT CIRCUIT MODEL - Circuit model (lumped, distributed, S-parameter, etc. ) - Limitations - Reference to similar models validated by measurement - A statement of the range of frequency over which the model is valid EIA JEPL26 96 3234b 0573745 838
