1、 JEDEC PUBLICATION Reliability Qualification of Semiconductor Devices Based on Physics of Failure Risk and Opportunity Assessment JEP148B (Revision of JEP148A, December 2004) JANUARY 2014 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been
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9、. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 148B -i- RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON P
10、HYSICS OF FAILURE AND RISK AND OPPORTUNITY ASSESSMENT Contents Page Introduction . ii 1 Scope . 1 2 References . 1 3 Terms and definitions . 2 4 Planning for quality and qualification: situation, approach and procedure 3 4.1 Application requirements 3 4.2 Qualification concepts 3 4.3 The Physics-of-
11、Failure concept . 4 4.4 The systematic procedure: the Risk - use of products of mature designs and technologies by extending the knowledge about their applicability in more demanding applications. Time-to-market requires efficient quality planning and confirmation Shortening time to-market period fo
12、rces one to consider - integration of qualification into the innovation process with early start of the qualification activities replacing qualification as a separate and sequential activity, - effective use of knowledge, i.e., applying existing results for qualification, - compatibility with simult
13、aneous engineering practices. Reliability qualification will refer to physics-of-failure knowledge As a consequence, the practices of qualifying products for reliability are changing - from reactive activities at the end of a development cycle applying uniform and predefined stress testing with gene
14、ric qualification plans - to measures deliberately integrated into the development cycle making proactive use of stricter physics-of-failure based testing with respect to the product construction and the use conditions of the application segment - to approaches to measure the robustness with respect
15、 to well specified application conditions. The approach taken is to: apply a systematic procedure which enables concentration on those product properties with respect to product construction and application conditions which really need to be qualified (part I), arrange the qualification methodology
16、to correspond to the relationships between designs; technology, manufacturing and product life phases at use conditions (part II). JEDEC Publication No. 148B Page 1 RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE AND RISK AND OPPORTUNITY ASSESSMENT (From JEDEC Board Ba
17、llot JCB-08-63, and JCB-13-58, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope The purpose of this procedure provides a consistent frame work for reliability qualification using the Physics-of-Failure (PoF) concept, wh
18、ich is flexible with respect to the requirements of the intended application and market, makes optimum use of the suppliers advance quality planning and demonstration results gained during design and development and applicable knowledge based on design and technology similarities. Planning quality a
19、nd reliability in advance and gaining reliability results with the progress of a design and development process is efficiently supported by a systematic procedure for risk and opportunity assessment. The qualification concept is based on customer - supplier partnership in order to achieve optimized
20、efforts. The methodology applies to the reliability qualification of semiconductor devices and the processes for their development and manufacturing. 2 References (informative) 1 M. Pecht, A. Dasgupta, Physics of Failure: An Approach to Reliable Product Development, IRW Final Report 95. 2 K. Upadhya
21、yula, A. Dasgupta, Physics-of-Failure Guidelines for Accelerating Qualification of Electronic Systems Quality and Reliability, Enging. Int. 14: 433-447 (1998). 3 L. Oshiro, R. Radojcic, A Design Methodology for CMOS VLSI Circuits, IRW Final Report 97. 4 W.H. Gerling, F.W. Wulfert, Qualification for
22、Reliability in Time-to-Market Driven Product Creation Processes, Int. Rel. Phys. Symp. 2001, Tutorial. 5 SAE standard J 1879, identical with ZVEI , Handbook for Robustness Validation of Semiconductor Devices in Automotive Applications, 2007 6 B. Purvee, R. Susko, J. McCullen, J. Veshinsky, Use Condi
23、tion Based Reliability Evaluation of New Package Technologies, , www.sematech.org/public/docubase/abstracts/3813axfr.htm. 7 P. McClusky, M-Pecht, S. Azarm, J, Pecht, Decreasing Time-to-Market Using Virtual Qualification, 1997 Proc. Inst. of Environmental Sciences. 8 W. Daukhser, D. Eaton, The Applic
24、ation of Finite Element Modeling to Qualification Testing - A Knowledge Based Approach, Sematech TCR 99. 9 R. Blish, N. Durrant, Semiconductor Device Reliability Failure Models, Sematech RTAB, 5/2000, http:/www.sematech.org/public/docubase/abstracts/3813axfr.htm. 10 JEDEC Publication 122, Failure Me
25、chanisms and Models for Semiconductor Devices. 11 A. Preussger, N. Lycoudes, R. Blish, S. Huber, T. Dellin, ISMI (Sematech) white paper 04024492A-TR, “ Understanding and Developing Knowledge-based Qualification of Silicon Devices”, (2004) 12 H. Keller and A. Preussger, “Robustness Validation”, Tutor
26、ial ESREF 2006 JEDEC Publication No. 148B Page 2 2 References (informative) (contd) 13 Handbook for Robustness Validation of Semiconductor Devices in Automotive Applications, ZVEI 2007 (content copy: SAE J1879) 14 Robustness Validation Manual, ZVEI 2010 3 Terms and definitions For the purpose of thi
27、s publication, the following terms and definitions apply. acceleration model: A mathematical formulation of the relationship of rate (speed) of a degradation mechanism or time-to-failure to stresses or use conditions. application requirements for quality and reliability: The quality and reliability
28、properties of the product required for the intended specified use conditions. defect, (physical): A physical anomaly that adversely affects function or performance. defect density: The number of defects on a chip divided by its area. design rules: The basic rules and regulations for circuit design w
29、ith electrical and geometrical parameters specified for the range of application conditions and time. mission profile: The simplified representation of all of the relevant conditions to which a device will be exposed in its intended application throughout the full life cycle. physics-of-failure (PoF
30、) concept: An approach to the design and development of reliable product to prevent failure, based on the knowledge of root cause failure mechanisms. NOTE The PoF concept is based on the understanding of - the relationships between requirements and the physical characteristics of the product and the
31、ir variation in the manufacturing processes, and - the reaction of product elements and materials to loads (stressors) and interaction under loads and their influence on the fitness for use with respect to the use conditions and time. qualification: The process of demonstrating that an entity is cap
32、able of meeting or exceeding the specified requirements. qualification requirements: The quality and reliability properties of the product suited to demonstrate compliance to the application requirements. reliability qualification: The process of demonstrating that an entity is capable of meeting or
33、 exceeding the specified reliability requirements, usually by tests using accelerating conditions and proven models. robustness: The capability of functioning correctly or not failing under varying application and production conditions. risk and opportunity assessment process: The systematic procedu
34、re intended to; 1) proactively avoid problems such as unfulfilled requirements, demands, and expectations, 2) take advantage of capabilities (opportunities) that may exceed the requirements for a given approach, and 3) initiate appropriate measures to exploit opportunities and avoid, reduce, or prev
35、ent risks that would influence the user. JEDEC Publication No. 148B Page 3 3 Terms and definitions (contd) Safe Operating Area (SOA): The parameter space which guarantees functionality within specification. service life: the total lifetime of a system. useful life (of an unrepairable unit): The time
36、 interval between the start of use of an unrepairable unit and its statistically expected failure in an application. validation: The process of confirming the verification process under use conditions. verification: The process of confirming that the specified requirements are fulfilled, excluding r
37、eliability requirements. wafer level reliability (WLR): The characterization of product or technology reliability on wafer level by applying stress to specific test structures. 4 Planning for quality and qualification: situation, approach and procedure 4.1 Application requirements The requirements o
38、f the customer or the application segments in general refer to: application conditions and time (use mission profile, service life), processing conditions at the equipment manufacturer, storage and transportation conditions, expected statistical reliability properties, e.g., tolerable early failure
39、rate and period. The different application segments vary concerning their system requirements, application conditions and planned time of use ranging from benign environments and short-term use to harsh environmental conditions and long-term application. This is represented e.g., by chip cards, mobi
40、le phones, consumer electronics, computers, automotive applications, telecom networks, each with individual use or mission profiles. Requirements are specified in terms of: robustness against external loads expected statistical reliability properties, e.g., tolerable early failure rate and period. 4
41、.2 Qualification concepts Qualification of products means to confirm their fitness for use as a result of appropriate processes for their realization. This includes: verification of their function and performance, validation in the system application (less for commodities), qualification for process
42、ability (OEM board assembly) and reliability. JEDEC Publication No. 148B Page 4 4.2 Qualification concepts (contd) There are two different approaches to the part qualification for processability and reliability: a) examination of the product as a “black box“ by comparing its properties to specified
43、requirements as “final inspection“ after product development at the manufacturer (or “incoming inspection” at the user). It is, in this sense, reactive, it adds, in general, an additional phase to development, and it hardly differentiates in giving focus on those issues which really need to be quali
44、fied, it applies for reliability the “stress test driven qualification“, which confirms a stress test capability by which “a certain level of quality/reliability“ can be expected in the application. The intention of this traditional method is to test for the existence of failure modes, which have be
45、en observed in application, by stress tests at elevated conditions. This means, it is mainly based on experience with products of matured technologies. The variable parameters of test and stress conditions are restricted to those, which can be set and varied from outside of the products. These are m
46、ainly electrical operational conditions within data sheet limits and environmental conditions. Also the control of the resulting internal stresses is limited or not feasible. The evaluation is essentially qualitative, as the relations between applied stress test conditions and lifetime at use condit
47、ions to be covered by tests are usually not established. Therefore the meaningfulness of results is questionable in case of new or changed materials or technologies. b) conclusive derivation of qualification targets and activities from application requirements and planned product construction in a p
48、roactive way as described in failure mechanism specific knowledge based qualification 11, 12, 13, and 14: it considers qualification as an integral part of design and development with early involvement in this process, i.e., starting in the definition phase and agreeing to requirements and checking
49、their feasibility; it makes extensive use of applicable results, e.g., by considering the technological and design properties common to all products or product elements of a technology (family) or results gained on similar products; it adjusts the qualification to the application conditions and the time period of the intended application on a quantitative level with knowledge of active stresses and potential failure mechanisms based upon the “Physics-of-Failure Concept”. 4.3 The Physics-of-Failure concept The Physics-of
