1、JEDEC PUBLICATION 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions JEP158 NOVEMBER 2009 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved t
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7、www.jedec.org Published by JEDEC Solid State Technology Association 2009 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge
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9、ntering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Publication No. 158 -i- 3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): IDENTIFYING, EVALUATING AND UNDERS
10、TANDING RELIABILITY INTERACTIONS Introduction To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies
11、. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Disclaimer The users attention is called to the possibility that compliance with this document may require use of an inv
12、ention covered by patent rights. By publication of this document, no position is taken with respect to the validity of this claim or of any patent rights in connection therewith. As of September 2009, the patent holder has neither assured nor precluded a willingness to grant a license under these ri
13、ghts on reasonable and nondiscriminatory terms to applicants desiring to obtain such a license. JEDEC Publication No. 158 -ii- JEDEC Publication No. 158 Page 1 Compliance with this section of the document may require requires U.S. Patent Applications No. 11/351,418 and 11/593,788. Users are advised
14、to assess exposure to patent rights in applying this publication. 3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): IDENTIFYING, EVALUATING AND UNDERSTANDING RELIABILITY INTERACTIONS (From JEDEC Board Ballot JCB-09-64, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reli
15、ability Qualification and Monitoring.) 1 Scope This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests provide guidance for qualifying new and modified technology/process/ product families, as well as individual solid state surface-mount p
16、roducts. This publication is intended as a guideline to describe the extension of the standard tests to three-dimensional (3D) chip structures that contain stacks of two or more chips that use through-silicon vias to connect from the front side to the back side of each chip. The main element of this
17、 extension is the addition of appropriate test structures to evaluate the reliability of the TSVs and other new features introduced in the fabrication of 3D products. This publication applies to vias-first process (TSV formation before completion of the silicon device fabrication), vias-middle (TSV
18、formed in the BEOL or prior to the BEOL process), and a vias-last process (TSV formation after completion of the silicon device fabrication). Although 3D TSV test structures may not be a prerequisite for silicon chip qualification, they are necessary if those chips are intended for use in 3D product
19、s. If the effects of 3D TSVs on a device technology placed in a specific packaging scheme are not known, there could be reliability concerns for that component (packaged part) that are not evident with standard component level test structures. Therefore, it is recommended to include 3D TSV test stru
20、ctures and associated testing and failure analysis to determine if there are any adverse effects on the assembly due to packaging. This publication covers only interaction between the 3D TSV component, the semiconductor package, and the semiconductor device. Interactions between the assembled compon
21、ent and a second level assembly are not covered. See JEP150 for information regarding assembled component reliability. The reliability stress tests referred to in this document have been found capable of stimulating and precipitating failures in components in an accelerated manner, but they should n
22、ot be used indiscriminately. Failures from each test should be examined for: a) potentially new and unique failure mechanisms b) situations where these tests/conditions may induce invalid or overstress failures. In either case, the set of reliability requirements, tests, and/or conditions should be
23、appropriately modified to properly include the new failure mechanisms and modes. This document does not relieve the supplier of the responsibility to meet internal or customer-specified qualification programs. JEDEC Publication No. 158 Page 2 Compliance with this section of the document may require
24、requires U.S. Patent Applications No. 11/351,418 and 11/593,788. Users are advised to assess exposure to patent rights in applying this publication. 2 Terms and Definitions 3D chip stack: Two or more chips vertically connected to form a unified electrical structure in a single package. assembled sta
25、te (of a component): The state of a component that has been attached to a second-level assembly. back-end-of-line (BEOL) (adj): Pertaining to the portion of the semiconductor processing line that creates the conductive lines carrying power and signals between devices and to the interface connecting
26、off-chip. back end of line (BEOL) (noun): The portion of the semiconductor processing line that creates the conductive lines carrying power and signals between devices and to the interface connecting off-chip. bond and assembly process (B level D interconnect: The structure that connects one chip in
27、 a 3D stack to another chip in that 3D stack. NOTE Examples of this structure include, but are not limited to, solder bumps and copper pads. chip-to-package interaction (CPI): For the purpose of this document, the interaction between stresses induced by the semiconductor package and the semiconducto
28、r chip whether alone or within the semiconductor 3D chip stack. chip-to-substrate-interconnect; level 1 (L1) interconnect: The structure that connects a chip to a substrate. NOTE 1 For the purpose of this document a “chip-to-substrate-interconnect” is referred to as an “interconnect”. NOTE 2 Example
29、s of this structure include, but are not limited to, solder bumps and copper columns. NOTE 3 Level 1 (L1) interconnect is not associated with JP 001 Foundry Level 1 Qualification (L1). dice: Plural of die. distance to neutral point (DNP): The physical distance from the stress-neutral point to the po
30、int of interest on the die, chip stack, or interposer. JEDEC Publication No. 158 Page 3 Compliance with this section of the document may require requires U.S. Patent Applications No. 11/351,418 and 11/593,788. Users are advised to assess exposure to patent rights in applying this publication. 2 Term
31、s and Definitions (contd) failure mechanism: The physical, chemical, electrical, or other process that has led to a nonconformance. NOTE 1 See JESD671, Component Quality Problem Analysis and Corrective Action Requirements. NOTE 2 A failure mechanism may be characterized by how a degradation process
32、proceeds including the driving force, e.g., oxidation, diffusion, electric field, current density. failure mode (general): The way in which a failure mechanism manifests itself in a failing component. NOTE Examples of failure modes are a visual blemish, a bent lead, a foreign particle or material, a
33、n incorrect dopant profile or grain size, a scratch, an electrical fault (open, short, leakage, inadequate slew rate or noise margin, stuck at high or low, etc.). far-back-end-of-line (FBEOL) (adj): Pertaining to the portion of the semiconductor processing line that creates the metal layer (e.g., th
34、e UBM or redistribution layer) and associated interconnect structures forming the connection between on-chip and off-chip wiring. far back end of line (FBEOL) (noun): The portion of the semiconductor processing line that creates the metal layer (e.g., the UBM or redistribution layer) and associated
35、interconnect structures forming the connection between on-chip and off-chip wiring. free-standing state (of a component): The state of a component that is not attached to the next level of assembly packaging. front-end-of-line (FEOL) (adj): Pertaining to the portion of the semiconductor processing l
36、ine that creates active devices, ending with the gate conductors. front end of line (FEOL) (noun): The portion of the semiconductor processing line that creates active devices, ending with the gate conductors. packaged device: A semiconductor device within an enclosure that allows electrical connect
37、ion to, and provides mechanical and environmental protection for, that device. second-level assembly: The attachment of a component to the next level of assembly packaging. stratum; tier: Each individual layer of silicon in a chip stack. through-silicon via (TSV): A conductive via that runs vertical
38、ly through a silicon chip and electrically connects structures on the top side and the bottom side of the chip. JEDEC Publication No. 158 Page 4 Compliance with this section of the document may require requires U.S. Patent Applications No. 11/351,418 and 11/593,788. Users are advised to assess expos
39、ure to patent rights in applying this publication. 2 Terms and Definitions (contd) under-bump metal (UBM): The metal layers located between the solder bump or column and the die. NOTE This is also known as the bump-limiting metals (BLM). via-first: A TSV formed before completion of the silicon devic
40、e fabrication NOTE These vias may be created before or during front-end-of-line (FEOL) but before back-end-of-line (BEOL) processing. They are created by etching them from the top side of the wafer, and are buried below the subsequent BEOL layers. The process allows for interconnects with a high den
41、sity. These vias connect circuits at the global or intermediate IC level. via-middle: A TSV formed after FEOL processing and prior to or during the BEOL process. NOTE A “via-middle” process is sometimes considered to be part of a “via-first” process. via-last: A TSV formed after the completion of th
42、e silicon device fabrication, specifically after the completion of both FEOL and BEOL layer processes. NOTE The TSVs connect circuits at the bond-pad level. 3 References 3.1 Informative references JEP122, Failure Mechanisms and Models for Silicon Semiconductor Devices. JEP131, Process Failure Modes
43、and Effect Analysis (FMEA). JEP150, Stress-test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components. JEP154, Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress. JEP156, Chip Package Interac
44、tion Understanding, Identification and Evaluation Guideline. Handbook of 3D Integration, Volume I and II, P. Garrou, C. Bower and P. Ramm, Ed, Wiley-VCH. JEDEC Publication No. 158 Page 5 Compliance with this section of the document may require requires U.S. Patent Applications No. 11/351,418 and 11/
45、593,788. Users are advised to assess exposure to patent rights in applying this publication. 3 References (contd) 3.2 Normative references JESD22, Reliability Test Methods for Packaged Devices. JESD47, Stress-Test-Driven Qualification of Integrated Circuits. JESD74, Early Life Failure Rate Calculati
46、on Procedure for Electronic Components. JESD85, Methods for Calculating Failure Rate in Units of FITs. JESD91, Method for Developing Acceleration Models for Electronic Component Failure Mechanisms. JESD94, Application Specific Qualification using Knowledge Based Test Methodology. J-STD-020, Joint IP
47、C/JEDEC Standard for Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface-Mount Devices. J-STD-033, Joint IPC/JEDEC Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface-Mount Devices. 4 Overview of TSV Chip Stack Manufacturing and Reliabilit
48、y 3D chip stacks are affected by the same stresses as single chips. However, in the 3D chip stack, there are extra silicon layers, called strata, and TSVs, which add more structures and complexity to the system (Figure 4-1 and Figure B-1). Instead of one plane of electrical inter-connections (from t
49、he chip to the package), there may be one or more additional planes of electrical inter-connections from one stratum in the stack to another stratum in the stack. The TSVs provide vertical intra-connections in through each stratum. Traditional CPI structures can be used to evaluate the inter-connections between strata in the 3D stack and between the chip stack and the package. New structures are used here to evaluate the TSV intra-connection. Figure 4-1 3D chip stack with TSVs and interconnections between strata in the stack Stratum 3 Chip to chip interconnect Stratum 1 Stratum
