1、JEDEC PUBLICATION Selection of Burn-In/Life Test Conditions and Critical Parameters for QML Microcircuits JEP163 SEPTEMBER 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of
2、Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and a
3、ssisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption m
4、ay involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents
5、 a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in c
6、onformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Docume
7、nts for alternative contact information. Published by JEDEC Solid State Technology Association 2015 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the indiv
8、idual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Ass
9、ociation 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 163 -i- SELECTION OF BURN-IN/LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS Contents PageForeword iiIntroducti
10、on ii1 Scope 12 References 13 Terms and definitions 24 Wafer Fabrication and Design Considerations 45 Burn-in Stress and Electrical Test Conditions Development 56 Life Test Stress and Electrical Test Conditions Development 10Annex A (informative) Example Burn-in Condition Evaluations 14Annex B (norm
11、ative)Burn-in and Electrical Measurement Requirements 19JEDEC Publication No. 163 -ii- Foreword This publication was developed as a guideline to assist manufacturers of integrated circuits (microcircuits) in defining the conditions for burn-in and life test of their products to meet the quality and
12、reliability performance requirements of MIL-PRF-38535 and the applicable Standard Military Drawing. Documentation of the manufacturers technical rationale in accordance with this guideline will also facilitate customer understanding and acceptance of the manufacturers Quality Management (QM) plan. I
13、ntroduction MIL-PRF-38535, in conjunction with MIL-STD-883, defines the basic screening requirements for compliant microcircuits. MIL-STD-883 Test Method 5004 specifies two independent burn-in conditions for Class Level S devices. A dynamic burn-in is performed for 240 hours at 125 C. A static or re
14、verse bias burn-in is performed for 72 hours at 150 C. Per Test Method 5004 the reverse bias burn-in is a requirement only when specified in the applicable device specification (i.e. Standard Military Drawing) and is recommended only for a certain MOS, linear or other microcircuits where surface sen
15、sitivity may be of concern. These requirements have been part of the military standards for decades and originated at a time when design rules and wafer fabrication processes were much less advanced than current state-of-the art technologies. With the advent of improved wafer fabrication processes,
16、Statistical Process Controls (SPC), Wafer Level Reliability (WLR), Circuit Design Tools, Design-For-Test (DFT) techniques, and modern simulation and characterization techniques, the presence of certain failure modes have been reduced and/or eliminated for certain wafer fabrication processes. However
17、, deep submicron and System On A Chip wafer fabrication processes have potentially greater transistor to transistor process variations; hence, they may have a greater need for burn-in and life test to evaluate and screen infant life mortality. Due to the current variation in geometry sizes and diffe
18、rent levels of technology maturity and circuit designs, the establishment of the appropriate burn-in/life test stress and test conditions must be evaluated in relation to each products wafer fabrication process and circuit design techniques. The stress conditions must demonstrate adequate Early Fail
19、ure detection and Intrinsic Failure Rate (IFR) performance that meets customer failure rate requirements. For example, a typical space application has a goal of 10 to 15 years operating life. JEDEC Publication No. 163 Page 1 SELECTION OF BURN-IN/LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML M
20、ICROCIRCUITS (From JEDEC Board Ballot JCB-15-29, formulated under the cognizance of the JC-13.2 Government Liaison Committee on Microelectronic Devices) 1 Scope This publication is intended as a guideline to develop and establish conditions for burn-in and life test of MIL-PRF-38535 QML integrated c
21、ircuits. These guidelines are intended to provide manufacturers with a consistent means of defining burn-in and life test stress and electrical test requirements acceptable to user organizations and for the development of Standard Military Drawings. The guidelines cover the entire design, wafer fabr
22、ication and manufacturing flows, including design and process awareness. Without design awareness (critical circuit blocks / functionality, etc.), burn-in / life test of an integrated circuit might be compromised, or it might dramatically shorten the devices life prior to system use. 2 References EE
23、E-INST-002, Instructions for EEE Parts Selection, Screening, Qualification, and Derating (NASA Goddard Space Flight Center) JEP122, Failure Mechanisms and Models for Semiconductor Devices JESD85, Methods for Calculating Failure Rates in Units of FITs MIL-HDBK-1331, Handbook for Parameters to be Cont
24、rolled for the Specification of Microcircuits (DLA Land and Maritime) MIL-PRF-38535, General Specification for Integrated Circuits (Microcircuits) Manufacturing (DLA Land and Maritime) MIL-STD-883, Test Method Standard Microcircuits (DLA Land and Maritime) JEDEC Publication No. 163 Page 2 3 Terms an
25、d definitions For the purposes of this standard, the terms and definitions given in the above references and the following apply: absolute maximum rated junction temperature: The maximum junction temperature of an operating device, as listed in its data sheet and beyond which damage (latent or other
26、wise) may occur; it is frequently specified by device manufacturers for a specific device and/or technology. NOTE Manufacturers may also specify maximum case temperatures for specific packages. absolute maximum rated voltage: The maximum voltage that may be applied to a device, as listed in its data
27、 sheet and beyond which damage (latent or otherwise) may occur; it is frequently specified by device manufacturers for a specific device and/or technology. acceleration factor (A, AF): For a given failure mechanism, the ratio of the time it takes for a certain fraction of the population to fail, fol
28、lowing application of one stress or use condition, to the corresponding time at a more severe stress or use condition. NOTE 1 Times are generally derived from modeled time-to-failure distributions (lognormal, Weibull, exponential, etc.). NOTE 2 Acceleration factors can be calculated for temperature,
29、 electrical, mechanical, environmental, or other stresses that can affect the reliability of a device. NOTE 3 Acceleration factors are a function of one or more of the basic stresses that can cause one or more failure mechanisms. For example, a plot of the natural log of the time-to-failure for a cu
30、mulative constant percentage failed (e.g., 50%) at multiple stress temperatures as a function of 1/kT, the reciprocal of the product of Boltzmanns constant in electronvolts per kelvin and the absolute temperature in kelvins, is linear if one and only one failure mechanism is involved. The best-fit l
31、inear slope is equal to the apparent activation energy in electronvolts. NOTE 4 The abbreviation AF is often used in place of the symbol A. JEDEC Publication No. 163 Page 3 3 Terms and definitions (contd) acceleration factor, temperature (AT): The acceleration factor due to changes in temperature. N
32、OTE 1 This is the acceleration factor most often referenced. The Arrhenius equation for reliability is commonly used to calculate the acceleration factor that applies to the acceleration of time-to-failure distributions for microcircuits and other semiconductor devices: AT= T1/T2= exp(Eaa/k)(1/T1 1/
33、T2) where Eaais the apparent activation energy (eV); k is Boltzmanns constant (8.62 105eV/K); T1 is the absolute temperature of test 1 (K); T2 is the absolute temperature of test 2 (K); T1is the observed failure rate at test temperature T1(h-1); T2is the observed failure rate at test temperature T2(
34、h-1). NOTE 2 The best-fit linear slope of a plot of the natural log of the time-to-failure as a function of 1/kT, the reciprocal of the product of Boltzmanns constant in electronvolts per kelvin and the absolute temperature in kelvins, is equal to the apparent activation energy in electronvolts. NOT
35、E 3 q= o AT, where qis the quoted (predicted) system failure rate at some system temperature Ts, ois the observed failure rate at some test temperature Tt, and ATis the temperature acceleration factor from Ttto Ts. activation energy (Ea): The excess free energy over the ground state that must be acq
36、uired by an atomic or molecular system in order that a particular process can occur. NOTE The activation energy is used in the Arrhenius equation for the thermal acceleration of physical reactions. The term “activation energy” is not applicable when describing thermal acceleration of time-to-failure
37、 distributions, e.g., in the Arrhenius equation for reliability; hence the need for the term “apparent activation energy”. apparent activation energy (Eaa): An energy value, analogous to activation energy, that can be inserted in the Arrhenius equation for reliability to calculate an acceleration fa
38、ctor applicable to changes with temperature of time-to-failure distributions. NOTE 1 An apparent activation energy should be associated with a specific failure mechanism and an observed time-to-failure distribution to calculate the acceleration factor for converting the observed failure rate to the
39、quoted failure rate at a different temperature. NOTE 2 An activation energy is a measure of the heat energy needed to establish the rate of reaction for a specific failure mechanism. The reaction rate and other contributing factors, e.g., radiation, voltage, humidity, magnetic fields, determine the
40、unique time-to-failure distribution for the modeled failure mechanism. NOTE 3 The apparent activation energy is empirically determined from the change in an observed time-to-failure distribution with temperature. JEDEC Publication No. 163 Page 4 3 Terms and definitions (contd) failures in time (FITs
41、): The number of failures per 109device hours. high-temperature forward-bias (HTFB) test: A static test configured to forward-bias at least a majority of the solid-state junctions of the devices operating at, or near, absolute maximum rated junction temperature and voltages. high-temperature reverse
42、-bias (HTRB) test: A static test configured to reverse-bias at least a majority of the solid-state junctions of the devices operating at, or near, absolute maximum rated junction temperature and voltages. NOTE For some CMOS circuits, any static state will reverse-bias approximately half the junction
43、s (others are zero-biased). recommended operating conditions: The operating conditions, such as supply voltage and junction temperature, at which a device is specified to operate in compliance with the applicable device specification or data sheet. NOTE 1 Maximum and minimum values are applicable; t
44、hese adjectives refer to the magnitudes. NOTE 2 The maximum recommended operating supply voltage is not the absolute maximum rated voltage, i.e., the voltage beyond which damage is likely. toggle coverage: The percentage of signals in a device that are toggled (transitioned Low to High and from High
45、 to Low) during one complete cycle (an entire sequence of applied signals). 4 Wafer Fabrication and Design Considerations The goal of burn-in is to screen early life defects. These defects are normally due to variation or anomalies within the wafer fabrication process or circuit design. The burn-in
46、stress needs to be negligible with regard to life time wear out mechanisms. Wafer fabrication defect density variation, ionic contamination sources, process variability, parametric performance variability, and other potential process features contribute to early life failures. The use of Statistical
47、 Process Controls (SPC) helps ensure the consistency of the wafer fabrication process. An FMEA (Failure Mode Effects Analysis) assessment in regards to design, transistor layout and interconnect technology in concert with the wafer fabrication process and the processes capabilities and limitations i
48、s needed to help identify potential early life failure modes and wear out mechanisms. JEDEC Publication No. 163 Page 5 4 Wafer Fabrication and Design Considerations (contd) The FMEA provides identification of those process/design features that need to be evaluated using wafer level reliability (WLR)
49、 assessments. This reliability assessment is needed to accelerate life time wear out mechanisms that cannot be determined without extensive long term stress testing. The device design shall then be reviewed in regards to Design for Test / Design for Burn-in for the controllability / observability of the mechanisms to be observed in order to develop the appropriate burn-in and life test conditions. There are many stresses that accelerate various failure mechanisms in silicon. Such stresses include temperature, voltage, frequency and current density. Accelera
