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9、ct JEDECPrinted in the U.S.A.All rights reservedJEDEC Publication No. 171Page 1GDDR5 MEASUREMENT PROCEDURES(From JEDEC Board Ballot JCB-13-55, formulated under the cognizance of the JC-42.3 Subcommittee on DRAM Memories.)1ScopeThis publication is to inform all industry participants of a unified proc
10、edure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5.This document provides the test methodology details on:1. CK and WCK Timings: tCK, tWCK, tCH/tCL, tWCKH/tWCKL, CK TJ/RJrms, CK and WCK Jitter2. CK and WCK Input Operating C
11、onditions: VIXCK, VIXWCK, VIDCK(ac), VIDWCK(ac), VIDCK(dc), VIDWCK(dc), CKslew, and WCKslew3. Data Input Timings: tDIVW, tDIPWNOTE The procedures described in this document are intended to provide information about the tests that will be used in JEDEC GDDR5 recommended measurement parameter. This te
12、sting is not a replacement for an exhaustive test validation plan.2 CK and WCK Timings 2.1 Test Setup 1. Probe differential at the WCK and WCK_c to the oscilloscope input channels. Connect one channel ve+ to WCK and ve- to WCK_c. NOTE Specs are defined “at the pin”; however this is difficult when im
13、plemented in a design and require probing at vias or probe points at some distance from the pin. An analysis needs to be done to determine best probe distance from the pin. It is recommended that probe points, termination and so forth be noted with the measurement results.Figure 1 CK and WCK Timings
14、 Measurement Setup differentialVssVssWCKWCK#Length (TL1)Length (TL0)GDDR5ControllerDifferential Probe+-JEDEC Publication No. 171Page 22.2 tCK and tWCK Measurement ProceduretCK and tWCK are calculated as the average clock period across any consecutive Ntopcycle window, where each clock period is calc
15、ulated from rising edge to rising edge. NOTE A single cycle can be less than tWCK(avg)min. spec. and greater than tWCK(avg)max. spec. Allowable jitter is a partner to these specifications.2.2.1 Test Procedure tWCK1. Perform scope and probe calibration as required by the equipment manufacturer. 2. Co
16、nnect one channel to WCK and WCK_c.3. Power up device under nominal condition (room temperature, VDD(nom). Before making the actual measurement, the scope is first conditioned (set sample rate, memory depth and vertical settings) for measurement using the clock signals provided by the nominal power
17、up condition of the device. 4. Using the signals provided by the device at nominal condition, the scope is readied for measurement (e.g., required setup for voltage settings, time capture, etc). he following is an example of steps taken:a. Recall factory setup on the scope. b. Set sample rate.c. Adj
18、ust the vertical settings so the signals will fill the scope screen but avoid clipping. This maximizes the vertical resolution of the scope for measurement.5. Measure from rising edge at 0V to next rising edge at 0V across Ntopcycles.Figure 2 tWCK Measurement ExampletWCK =Nj 1tWCK/ N()where N=NtopjJ
19、EDEC Publication No. 171Page 32.2.1 Test Procedure tWCK (contd)6. Calculate tWCK. 7. Record values and conditions and compare against specification.NOTE 1 Vdd/Vddq Supply voltage used in measurement.NOTE 2 Temperature Ambient, or set temperature used in measurement.NOTE 3 Probe point TL0/TL1 TL0 Tra
20、ce length/location and characteristics of trace for WCK, TL1 Trace length/location and characteristics of trace for WCK_c.NOTE 4 Termination ODT enable, disable, or external Designate the type of termination used.NOTE 5 Termination value termination resistance.NOTE 6 Measured Value Value measured as
21、 per procedure.tW CK =Nj 1tW CK/ N()where N=NtopjVdd/Vddq1Temperature2Probe point TL0/TL13Termination ODT enable, disable, or external4Termination value5ZQ Measured value6JEDEC Publication No. 171Page 42.3 tCH/tCL and tWCKH/tWCKL Measurement ProceduretCH and tWCKH are defined as the average high pul
22、se width, as calculated across any consecutive Ntophigh pulses. tCL and tWCKL are defined as the average low pulse width, as calculated across any consecutive Ntoplow pulse. 2.3.1 Test Procedure tCK/tCL and tWCKH/tWCKL1. Perform scope and probe calibration as required by the equipment manufacturer.
23、2. Connect one channel to WCK and another to WCK_c.3. Power up device under nominal condition (room temperature, VDD(nom). Before making the actual measurement, the scope is first conditioned (set sample rate, memory depth and vertical settings) for measurement using the clock signals provided by th
24、e nominal power up condition of the device. 4. Using the signals provided by the device at nominal condition, the scope is readied for measurement (e.g., required setup for voltage settings, time capture, etc). he following is an example of steps taken:a. Recall factory setup on the scope. b. Set sa
25、mple rate.c. Adjust the vertical settings so the signals will fill the scope screen but avoid clipping. This maximizes the vertical resolution of the scope for measurement.5. Measure from rising edge to falling edge at 0V for tCH and from falling edge to rising edge at 0V for tCL across Ntopcycles.t
26、CH = / (N*tCK(avg)( )where N=NtopjtCL = / (N*tCK(avg)()where N=Ntopj=Nj 1tCH=Nj 1tCLtWCKH = / (N*tCK(avg)()where N=NtopjtWCKL = / (N*tCK(avg)()where N=Ntopj=Nj 1tWCKH=Nj 1tWCKLJEDEC Publication No. 171Page 52.3.1 Test Procedure tCK/tCL and tWCKH/tWCKL (contd)Figure 3 tCH/tCL Measurement Example6. Ca
27、lculate tCH/tWCKH and tCL/tWCKL. 7. Record values and compare to specification.NOTE 1 Vdd/Vddq Supply voltage used in measurement.NOTE 2 Temperature Ambient, or set temperature used in measurement.NOTE 3 Probe point TL0/TL1 TL0 Trace length/location and characteristics of trace for WCK, TL1 Trace le
28、ngth/location and characteristics of trace for WCK_c.NOTE 4 Termination ODT enable, disable, or external Designate the type of termination used.NOTE 5 Termination value termination resistance.NOTE 6 Measured Value Value measured as per procedure.tCH = / (N*tCK(avg)()where N=NtopjtCL = / (N*tCK(avg)(
29、)where N=Ntopj=Nj 1tCH=Nj 1tCLtWCKH = / (N*tCK(avg)()where N=NtopjtWCKL = / (N*tCK(avg)()where N=Ntopj=Nj 1tWCKH=Nj 1tWCKLVdd/Vddq1Temperature2Probe point TL0/TL13Termination ODT enable, disable, or external4Termination value5ZQ Measured Value6JEDEC Publication No. 171Page 62.4 CK and WCK Jitter Mea
30、surement ProcedureJitter for WCK and CK clocks are defined for N-cycle half-period jitter. TIE is measured across Mjtr half-cycles. TJN and RJN(rms) are calculated for each N-cycle half-period up to Ntop at the tested Bit Error Ratio (BER). Table 1 Key Jitter Characterization ParameterFor CK and WCK
31、 clocks, the maximum allowable jitter information can be measured and reported for N-cycle Half Period jitter as shown in Table 2. Refer to vendor specified values for application speed and PLL on or off case. The conditions involving temperature, VDD, and VDDQ are all recommended to be determined a
32、nd reported along with the jitter results. Table 2 Maximum Allowable Clock Input Jitter for N-Cycle Half Period Jitter tCK/tWCK = tbd GhzTemp = tbd, VDD = tbd, VDDQ = tbd2.4.1 Test Procedure WCK Jitter1. Perform scope and probe calibration as required by the equipment manufacturer. 2. Connect one ch
33、annel to WCK and WCK_c.3. Power up device under nominal condition (room temperature, VDD(nom). Before making the actual measurement, the scope is first conditioned (set sample rate, memory depth and vertical settings) for measurement using the clock signals provided by the nominal power up condition
34、 of the device. 4. Using the signals provided by the device at nominal condition, the scope is readied for measurement (e.g., required setup for voltage settings, time capture, etc). The following is an example of steps taken:a. Recall factory setup on the scope. b. Set sample rate.c. Adjust the ver
35、tical settings so the signals will fill the scope screen but avoid clipping. This maximizes the vertical resolution of the scope for measurement.JEDEC Publication No. 171Page 72.4.1 Test Procedure WCK Jitter (contd)5. Measure at 0V crossing point from actual edge vs ideal for each 0 to Mjtr half-cyc
36、les. Ideal half-period is defined as a measured average creating a TIE mean of zero. Fk= tk- trefk, k = 0,.,Mjtr.Figure 4 Measure WCK and CK from Ideal6. Separate TIE sequence F into DJ and RJ sequences. After separation, each point in TIE can be represented as: Fk= DJk+ RJk, k=0,.,Mjtr, see Figure
37、5.NOTE There are several methods to separate RJ and DJ. Any method to separate RJ and DJ in to their index values is an acceptable method.)Figure 5 Calculate Rj for each index k 7. Calculate differences for FNfor TIE F and RJNfor RJ for each N half-cycle. FNk= Fk- Fk-Nand RJNk= RJk- RJk-Nwhere k=N,M
38、jtr; N=1,.,NtopIdealVariationK=1VariationK=2Ideal IdealVariationK=MjtrTIE blueRj redJEDEC Publication No. 171Page 82.4.1 Test Procedure WCK Jitter (contd)Figure 6 Calculate FNand RJN8. Calculate the standard deviation for RJ for each N from step 7 to get RJN(rms). 9. Calculate DJddN(for each N = 1Nt
39、op) using max FNand min FNfrom step 7 and RJN(rms) from step 9. Djdd = max(FN) - min(FN) - 2*Q(1/Mjtr)*s(RJN) where Q(x) = sqrt(2)*erfc-1(2x)10. Calculate TJN (for each N = 1Ntop). TJN= DJddN+ 2*Q(BER)*s(RJN). 11. Record values and compare to specification.NOTE 1 Vdd/Vddq Supply voltage used in meas
40、urement.NOTE 2 Temperature Ambient, or set temperature used in measurement.NOTE 3 Probe point TL0/TL1 TL0 Trace length/location and characteristics of trace for WCK, TL1 Trace length/location and characteristics of trace for WCK_c.NOTE 4 BER Tested bit error ratio.NOTE 5 tCK/tWCK CK ir WCK cycle tim
41、e tested.NOTE 6 TJN Total jitter from step 10 for each N half-cycle.NOTE 7 RJN(rms) RMS Random Jitter from step 8 for each N half-cylce.NVdd/Vddq1Temerature2Probe point TL0/TL13BER4tck/tWCK5TJN6RJN(rms)712345678.N topJEDEC Publication No. 171Page 93 CK and WCK Input Operating Conditions3.1 Test Setu
42、p1. Probe dual single ended at the WCK and WCK_c to the oscilloscope input channels. Connect one channel to WCK and Vss and another to WCK_c and Vss. Vid is measured on a differential signal. Vid can be connected the same and then a math function to measure a differential signal or connected as show
43、n in figure 8. Note: Specs are defined “at the pin”; however this is difficult when implemented in a design and require probing at vias or probe points at some distance from the pin. An analysis needs to be done to determine best probe distance from the pin. There are variable termination possibilit
44、ies ODT, external termination, or no termination. There are also variable loading possibilities and sharing between die. It is recommended that probe points, termination and so forth be noted with the measurement results. Figure 7 CK and WCK Input Operating Conditions Measurement Setup - Dual Single
45、d EndedFigure 8 Alternative for Vid Measurements differentialVssVssWCKWCK#Length (TL1)Length (TL0)GDDR5ControllerVssVssWCKWCK#Length (TL1)Length (TL0)GDDR5ControllerDifferential Probe+-JEDEC Publication No. 171Page 103.2 VIXCK(ac) and VIXWCK(ac) Measurement ProcedureVIXWCK is the clock input crossin
46、g point voltage. For CK/CK_c, the crossing point must be within +/- 0.12V of VREFC. For WCK/WCK_c, the crossing point must be within +/- 0.10V of VREFD. Figure 9 Definition for VIX(ac)References: 1 GDDR5 SGRAM specification (rev G) Figure 823.2.1 Test Procedure1. Perform scope and probe calibration
47、as required by the equipment manufacturer. 2. Connect two active probes to oscilloscope channels. 3. Connect one channel to WCK and another to WCK_c.4. Power up device under nominal condition (room temperature, VDD(nom). Before making the actual measurement, the scope is first conditioned (set sampl
48、e rate, memory depth and vertical settings) for measurement using the clock signals provided by the nominal power up condition of the device. 5. Using the signals provided by the device at nominal condition, the scope is readied for measurement (e.g., required setup for voltage settings, time captur
49、e, etc). The following is an example of steps taken:a. Recall factory setup on the scope. b. Set sample rate.c. Adjust the vertical settings so the signals will fill the scope screen but avoid clipping. This maximizes the vertical resolution of the scope for measurement.6. Turn on sin(x)/x interpolation. 7. For CK, measure the “mean” voltage of VREFC and for WCK, measure the
