1、JEDEC PUBLICATION DDR4 PROTOCOL CHECKS JEP175 JULY 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC lega
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9、 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 175 -i- DDR4 PROTOCOL CHECKS Contents PageForeword iiIntroduction ii1 Scope 12 Normative references 13 Terms and definitions 14 DDR4 Protocol Checks Based on Timing Between Events 25 DDR4 Protocol Check
10、s Based on Ordering of Events 8JEDEC Publication No. 175 -ii- Foreword The intended use of this document is for the validation and debug of DDR4 based designs. This document contains protocol checks, sometimes referred to as memory access rules or protocol violations. These protocol checks can be im
11、plemented in simulation for pre-silicon verification or implemented in a protocol analyzer, logic analyzer, or oscilloscope for post silicon verification. The contained list of protocol checks is by no means the definitive list of protocol checks as other checks not contained in this list probably d
12、o exist. This document was created by the JC-40.5 JEDEC Committee. This document is subservient to the JEDEC JESD79-4B DDR4 Specification and the SPD Specification, JESD 21-C Section Title: Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules. JEDEC Publication No. 175 Page 1 DDR4 PROTOCOL C
13、HECKS (From JEDEC Board Ballot JCB-17-17, formulated under the cognizance of the JC-40.5 Subcommittee on Logic Validation and Verification.) 1 Scope This document contains a list of checks that can be used during the verification or debug stages of development to check that accesses to a DDR4 DRAM a
14、dhere to JESD79-4B. These checks are derived from JESD79-4B. The intent of this document is not to supplant the JESD79-4B document, but to help consolidate the checks into a single easy to read document. This document was not intended to indicate how a protocol check measurement would be made, but w
15、hat measurement would be made. The how can differ based on the testing requirements or the equipment at hand. This document is not a definitive list as other DDR4 protocol checks do exist and can be added to this document during subsequent revisions. 2 Normative reference JESD79-4B, DDR4 SDRAM Stand
16、ard. 3 Terms and definitions For the purposes of this document, the following terms and definitions are used in this document. Symbol: A shorthand notation per JESD79-4B for the Parameter. NOTE Where the cell is grayed out, there is no official JEDEC parameter currently defined. However the equation
17、 is defined. Parameter: A text description from JESD79-4B describing the time between events targeting the DDR4 DRAM. Violation Criteria: in formula format is derived from the JESD79-4B specification. This is the protocol check. It is written such that if the condition is satisfied the protocol chec
18、k fails and a violation exists. Reference: A guide to the reader of where to look in JESD79-4B for more information on this protocol check. By no means is the reference exhaustive as the Parameter may be listed in many places. This is meant to be a starting point for the reader. Units: How the proto
19、col check will be measured. Notes: Guidance as to special cases that concern that particular check and can be found in JESD79-4B. JEDEC Publication No. 175 Page 2 4 DDR4 Protocol Checks based on Timing between events In general, the DDR4 specification details commands and the allowable time between
20、those commands targeted to the DDR4 DRAM. Generally speaking, those commands cannot be too close or too far apart in time. A protocol check is the measurement to ensure that this is adhered to. Parameter Symbol Violation Criteria (Formula) Reference Units Notes Read to Read Same Bank Group Write to
21、Write Same Bank Group MPR page x to MPR page x (where x = 1,2 or 3) tCCD_L Measurement is less than tCCD_Lmin. tCCD_Lmin = MAX(tCCD_LnCK, ROUNDUP(tCCD_Lns/tCKns) -.025) Table 14, Table 132, Table 133, Figure 60, Figure 61, Section 4.10.3, 4.25.7 nCK 1,4 Read to Read Different Bank Group Write to Wri
22、te Different Bank Group MPR page 0 to MPR page 0 tCCD_S Measurement is less than tCCD_Smin. Table 132, Table 133, Figure 60, Figure 61, Figure 82, Figure 83, Figure 117, Figure 118, Section 4.10.3, 4.25.7 nCK 1 Read to Write Same Bank Group Read to Write Different Bank Group Measurement is less than
23、 CL - CWL + RBL/2 +1tCK + tWPRE WL+BL/2 +1tCK+tWPRE Section 4.25.6, Figure 84 nCK 1,3 Write to Read Same Bank Group Measurement is less than CWL + WBL/2 + MAX(tWTR_LnCK, ROUNDUP(tWTR_Lns/tCKnS) -.025) Section 4.25.6, Table 132, Table 133, Figure 65 nCK 1,3,4 Write to Read Different Bank Group Measur
24、ement is less than CWL + WBL/2 + MAX(tWTR_SnCK, ROUNDUP(tWTR_SnS/tCKnS) -.025) Section 4.25.6, Table 132 and Table 133, Figure 64 nCK 1,3,4 Activate to Activate Same Bank Group tRRD_L Measurement is less than tRRD_Lmin. tRRD_Lmin = MAX(tRRD_LnCK, ROUNDUP(tRRD_Lns/tCKnS) -.025) Table 132, Table 133,
25、Figure 62 nCK 1,2,4 Activate to Activate Different Bank Group tRRD_S Measurement is less than tRRD_Smin. tRRD_Smin = MAX(tRRD_SnCK, ROUNDUP(tRRD_Sns/tCKns) -.025) Table 132,133, Figure 62 nCK 1,2,4 Greater than 4 Activate commands window tFAW Measurement is less than tFAWmin. tFAWmin = MAX(tFAWnCK,
26、ROUNDUP(tFAWns/tCKns)-.025) Table 132, Table 133, Figure 63 nCK 1,2,4 JEDEC Publication No. 175 Page 3 Parameter Symbol Violation Criteria (Formula) Reference Units Notes READ to PRE or PREA to the same Bank Measurement is less than MAX(tRTPnCK, ROUNDUP(tRTPns/tCKns)+ AL Section 4.24.3, Figure 98,Fi
27、gure 100 Table 132, Table 133 nCK 1,3,7 WR to PRE or PREA to the same Bank If both DM and CRC are enabled Measurement is less than WL + BL/2 + ROUNDUP(tWRnS/tCKns) -.025) WL + BL/2 + MAX(tWR_CRC_DMnCK, ROUNDUP(tWR_CRC_DMnS/tCKns) Figure 131, Section 4.25.5, Table 132, Table 133 nCK 1,3,7 DLL locking
28、 time: DLL Reset (MR0 b8) to any command requiring a locked DLL or CKE low. Commands requiring a locked DLL; RD, RDS4, RDS8, RDA, RDAS4, RDAS8 tDLLK Measurement is less than tDLLKmin. Table 14, Table 132, Table 133, Section 3.3.1, Section 4.27, Figure 6 nCK 1 Mode Register Set command cycle time: MR
29、S to MRS Exceptions: Gear Down Mode, C/A Parity Latency Mode, Per DRAM Addressability Mode, VrefDQ training value, mode and range, CS to Command/Address Latency Mode tMRD Measurement is less than tMRDmin. Table 132, 133. Figure 8, Section 3.4.1 nCK 1 Mode Register Command update delay: MRS to non-MR
30、S Command or ODT high Exceptions are listed in Note 2 Figure 9. tMOD Measurement is less than tMODmin. tMOD = MAX(tMODnCK, ROUNDUP(tMODns/tCKns) Table 132,133, Section 3.4.1, Figure 9, Figure 11 ODT reference 4.7.2 and Figure 15 nCK 1,7 Powerup and Reset calibration time: 1st ZQCL after Reset Low to
31、 High to any Command, ODT high, or CKE Low tZQinit Measurement is less than tZQinitmin. Table 132, Table 133, Figure 6, Figure 26 nCK 1 Normal Operation full calibration time: All but the 1st ZQCL after Reset Low to High to any Command, ODT high, CKE Low tZQoper Measurement is less than tZQopermin.
32、Table 132, Table 133, Figure 26 nCK 1 Normal Operation short calibration time: Time from ZQCS to any Command, ODT high, CKE Low tZQCS Measurement is less than tZQCSmin. Table 132, Table 133, Section 4.12.1, Figure 26 nCK 1 JEDEC Publication No. 175 Page 4 Parameter Symbol Violation Criteria (Formula
33、) Reference Units Notes RESET_n Low to High, then CKE Low to High to a valid Command tXPR Measurement is less than tXPRmin. tXPRmin = MAX(tXPRnCK, ROUNDUP(tRFCmin+10ns)/tCKns)-.025) Table 24, Table 132, Table 133, Figure 6, 7, Section 3.3.1 nCK 1,4 SRX to Commands not requiring a locked DLL Commands
34、 not requiring a locked DLL: ACT, PRE, PREA, REF, SRE, PDE,WRITE On Self-Refresh Exit DESELECT commands must be issued on every clock edge occurring during the tXS period. tXS Measurement is less than tXSmin. tXSmin = ROUNDUP(tRFCmin+10ns)/tCKns)-.025) Table 24, Table 132 and Table 133,Figure 11, Fi
35、gure 12, Section 4.4.3 Section 4.4.2, 4.27Note 8: Section 4.2nCK 1,4 SRX to any command not requiring a locked DLL in self refresh ABORT Commands not requiring a locked DLL: ACT, PRE, PREA, REF, SRE, PDE, WRITE Disable this check if MR4 A9 is not set (Disable Self Refresh Abort) tXS_ ABORT Measureme
36、nt is less than tXS_ABORTmin. tXS_ABORTmin = ROUNDUP(tRFC4+10ns)/tCKns)-.025) Table 24, Table 132 and Table 133,Figure 11, Figure 12, Section 4.4.3 Section 4.4.2, 4.27Section 3.5 nCK 1,4 SRX to ZQCL, ZQCS and MRS tXS_ FAST Measurement is less than tXS_FAST. tXS_FASTmin = ROUNDUP(tRFC4+10ns)/tCKns) T
37、able 132 and Table 133, Section 4.4.2 nCK 1,7 SRX to Commands requiring a locked DLL, READ or CKE Low or ODT High (synchronous ODT Commands) tXSDLL Measurement is less than tXSDLLmin tXSDLL = tDLLK(min) Table 132 and Table 133, Section 4.27 #2, Figure 146, Note 8 Section 4.2nCK 1 Exit Power Down wit
38、h DLL on to any valid Command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Power Down to ODT =1: MR5 A5=0 (ODT enabled) tXP Measurement is less than tXPmin. tXPmin = MAX(tXPnCK, ROUNDUP(tXPns)/tCKns) Table 132 and Table 133. Figure 45, Figure 46, Figure 148,
39、Table 56 Table 132 and Table 133 Figure 184 nCK 1,7 JEDEC Publication No. 175 Page 5 Parameter Symbol Violation Criteria (Formula) Reference Units Notes Even Parity is present on PAR, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0, and C0-C2 for 3DS. Only when MR5 A2:0 is NOT 000 On
40、ly when DLL mode is enabled ODD number of 1s present when Parity Enabled. Section 2.7, Table 13, Section 3.5 Section 4.5 integer number 3 Minimum CKE low width for Self refresh entry to exit timing This is the minimum amount of time the DRAM must stay in Self Refresh tCKESR Measurement is less than
41、tCKESRmin. tCKESRmin = tCKEmin + 1nCK Table 132 and Table 133, Figure 146 Section 4.27 nCK 1 CKE minimum pulse width (low and high) tCKE Measurement is less than tCKEmin. tCKEmin = MAX(tCKEnCK, ROUNDUP(tCKEns)/tCKns) Table 132 and Table 133 and Note 31 and Note 32. Figure 158 nCK 1,7 Power Down entr
42、y to exit timing minimum tPDmin Measurement is less than tPDmin. tPDmin = MAX(tCKEnCK, ROUNDUP(tCKEns)/tCKns) Table 132 and Table 133. Figure 45, Figure 158 nCK 1,7 Power Down entry to exit timing maximum ODT must be stable prior to Power Down entry and remain stable throughout tPDmax Measurement is
43、 greater than tPDmax. tPDmax=Roundup (9*tREFIns)/tCKns) Table 132 and Table 133. Figure 45, Figure 158 Figure 148, Figure 149 nCK 1,7 Timing of ACT command to Power Down entry tACTPDEN Measurement is less than tACTPDENmin. Table 132 and 133, Figure 155 nCK 1 Timing of PRE or PREA command to Power Do
44、wn entry tPRPDEN Measurement is less than tPRPDENmin. Table 132 and 133. Figure 156 nCK 1 Timing of RD or RDA command to Power Down entry tRDPDEN Measurement is less than tRDPDENmin. tRDPDENmin = RL + 4 + 1 Table 132 and 133. Figure 150 nCK 1 Timing of WR command to Power Down entry (BL8OTF, BL8MRS,
45、 BC4OTF) tWRPDEN Measurement is less than tWRPDENmin. tWRPDENmin = WL + 4 + ROUNDUP(tWRns/tCKns)-.025) Table 132 and 133. Figure 152 nCK 1,4 JEDEC Publication No. 175 Page 6 Parameter Symbol Violation Criteria (Formula) Reference Units Notes Timing of WRA command to Power Down entry (BL8OTF, BL8MRS,
46、 BC4OTF). WR in clock cycles as programmed in MR0 tWRAPDEN Measurement is less than tWRAPDENmin. tWRAPDENmin = WL + 4 + WR + 1 Figure 151, Table 132 and Table 133 Note 5 nCK 1 Timing of REF command to Power Down entry tREFPDEN Measurement is less than tREFPDENmin. tREFPDENmin = tREFPDENmin Table 132
47、 and Table 133. Figure 154 nCK 1 Timing of MRS command to Power Down entry tMRSPDEN Measurement is less than tMRSPDENmin. tMRSPDENmin = tMOD(min) Table 132 and Table 133. Figure 157 nCK 1 Activate to PRE command period Minimum tRASmin Measurement is less than tRASmin tRASmin = ROUNDUP(tRASminns/tCKn
48、s)-.025) Tables 107-113 nCK 1,4 Activate to PRE command period Maximum tRASmax Measurement is greater than tRASmax tRASmax = ROUNDUP(9*tREFIns/tnCKns) Tables 107 - 113 nCK 1,7 ACT to Read or Write Delay Time tRCD Measurement is less than tRCD tRCD = ROUNDUP(tRCDns/tCKns)-.025) Tables 107 - 113 nCK 1
49、,4 ACT to ACT or REF command period tRC Measurement is less than tRC tRC = ROUNDUP(tRCns/tCKns)-.025) Tables 107 - 113 nCK 1,4 REF to a non-Deselect Command tRFC1, tRFC2, tRFC4 Measurement is less than tRFCxmin tRFCx = ROUNDUP(tRFCxns/tCKns)-.025) Section 4.26, 4.9.2, Table 24, 132, 133. Figure 143 nCK 1,5,4 Average Refresh Interval tREFI1, tREFI2, tREFI4 Measurement equal or less than tREFIx measured over 8192 intervals with a rolling w
