1、JEDEC PUBLICATION Guide to Standards and Publications Relating to Quality and Reliability of Electronic Hardware JEP70C (Revision of JEP70B, October 1999) OCTOBER 2013 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed,
2、and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeab
3、ility and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without r
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5、EC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately becom
6、e an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to
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9、ontact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 70C i GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONI
10、C HARDWARE Contents Page Foreword ii Introduction ii 1 Scope 1 2 Normative references 1 3 Listing of quality and reliability standards and publications 2 3.1 Electrical tests - methods 2 3.2 ESD control - measurement, handling, symbol General Instructions and Index of Tests IEC-60068 Basic Environme
11、ntal Testing Procedures EIAJ ED-4701 Environmental and Endurance Test Methods for Semiconductor Devices IEC-60721 Classification of Environmental Conditions JEP79 Life Test Methods for Photoconductive Cells JEP110 Guidelines for the Measurement of Thermal Resistance of GaAs FETS JEP119 Procedure for
12、 Executing SWEAT JEP121 Requirement for Microelectronic Screening and Test Optimization JEP122 Failure Mechanisms and Models for Silicon Semiconductor Devices JEP150 Stress-Test-Driven Qualification Of And Failure Mechanisms Associated With Assembled Solid State Surface-Mount Components JEP153 Chara
13、cterization And Monitoring Of Thermal Stress Test Oven Temperatures JESD22-A100 Cycled Temperature Humidity Bias Life Test JESD22-A101 Steady State Temperature Humidity Bias Life Test JESD22-A102 Accelerated Moisture Resistance - Unbiased Autoclave JESD22-A103 High Temperature Storage Life JESD22-A1
14、04 Temperature Cycling JESD22-A105 Power and Temperature Cycling JESD22-A106 Thermal Shock JESD22-A107 Salt Atmosphere JESD22-A108 Temperature, Bias, and Operating Life JESD22-A109 Hermeticity JESD22-A110 Highly Accelerated Temperature and Humidity Stress Test (HAST) JESD22-A113 Preconditioning of P
15、lastic Surface-Mount Devices prior to Reliability Testing JESD28 A Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress JESD33 Standard Method for Measuring and Using the Temperature Coefficient of Resistance to Determine the Temperature of a Metallization Line JE
16、SD35 Procedure for Wafer-Level Testing of Thin Dielectrics JESD37 Standard Lognormal Analysis of Uncensored Data, and of Singly Right-Censored Data Utilizing the Persson and Rootzen Method JESD60 A Procedure for Measuring P-Channel MOSFET Hot-Carrier-Induced Degradation at Maximum Gate Current Under
17、 DC Stress JEDEC Publication No. 70C Page 10 3.8 Reliability Testing Methods (contd) JESD61 Isothermal Electromigration Test Procedure JESD63 Standard Method for Calculating the Electromigration Model Parameters for Current Density and Temperature JESD74 Early Life Failure Rate Calculation Procedure
18、 For Semiconductor Components J-STD-020 Moisture/Reflow Sensitivity Classification for Plastic Integrated Circuit Surface Mount Devices MIL-HDBK-814 Ionizing Dose and Neutron Hardness Assurance Guidelines for Microcircuits and Semiconductor Devices FSC 59GP MIL-STD-750 Test Methods for Semiconductor
19、 Devices FSC 5961 MIL-STD-790 Established Reliability and High Reliability Qualified products List (QPL) System for Electrical, Electronic, and Fiber Optic Part Specification MIL-STD-883 Test Methods Standard Microcircuits TECHAMERICA SSB-1.002 Environmental Tests and Associated Failure Mechanisms 3
20、.9 Visual and Mechanical Testing Methods Number Title AE -Q100-001 Wire Bond Shear Test AEC-Q100-005 Non-Volatile Memory Program/Erase Endurance, Data Retention, and Operational Life Test AEC-Q100-006 Electro-Thermally Induced Parasitic Gate Leakage Test (GL) AEC-Q100-007 Fault Simulation and Test G
21、rading AEC-Q100-008 Early Life Failure Rate (ELFR) AEC-Q100-009 Electrical Distribution Assessment AEC-Q100-010 Solder Ball Shear Test AEC-Q100-012 Short Circuit Reliability Characterization of Smart Power Devices for 12V Systems AEC-Q101-003 Wire Bond Shear Test AEC-Q101-004 Miscellaneous Test Meth
22、ods AEC-Q101-006 Short Circuit Reliability Characterization of Smart Power Devices for 12V Systems AEC - Q200-001 Flame Retardance Test AEC - Q200-003 Beam Load (Break Strength) Test AEC - Q200-004 Measurement Procedures for Resettable Fuses AEC - Q200-005 Board Flex / Terminal Bond Strength Test JE
23、DEC Publication No. 70C Page 11 3.9 Visual and Mechanical Testing Methods (contd) AEC - Q200-006 Terminal Strength (SMD) / Shear Stress Test AEC - Q200-007 Voltage Surge Test IEC 60695-1-11 Fire Hazard Testing IPC J-STD-004 Requirements for Soldering Fluxes IPC J-STD-006 Requirements for Electronic
24、Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications JEITA ED-4702 Mechanical Stress Test Methods for Semiconductor Surface Mounting Devices JEP84 Recommended Practice for Measurement of Transistor Lead Temperature JEP110 Guidelines for the Measurement of
25、 Thermal Resistance of GaAs FETS JEP114 Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification JEP121 Requirement for Microelectronic Screening and Test Optimization JEP156 Chip-Package Interaction Understanding, Identification And Evaluation JESD9 Metal
26、Package Specification for Microelectronic Packages and Covers JESD22-B100 Physical Dimensions JESD22-B101 External Visual JESD22-B102 Solderability JESD22-B103 Vibration, Variable Frequency JESD22-B104 Mechanical Shock JESD22-B105 Lead Integrity JESD22-B106 Resistance to Solder Shock for Through-Hol
27、e Mounted Devices JESD22-B107 Marking Permanency JESD22-B108 Coplanarity Test for Surface-Mount Semiconductor Devices JESD22-B111 Board Level Drop Test Method of Components for Handheld Electronic Products JESD22-B115 Solder Ball Pull JESD22-B116 Wire Bond Shear Test JESD22-B117 Solder Ball Shear MI
28、L-STD-750 Test Methods for Semiconductor Devices MIL-STD-883 Test Methods and Procedures Microcircuits UL 94 Tests for Flammability of Plastic Materials for Parts in Devices and Appliances UL1694 UL Standard for Safety Tests for Flammability of Small Polymeric Component Materials JEDEC Publication N
29、o. 70C Page 12 3.10 PB Component Application Assembly, Soldering, Board Level Testing Number Title IPC A-600 Acceptability of Printed Boards IPC A-610 Acceptability of Electronic Assemblies JEP154 Guideline For Characterizing Solder Bump Electromigration Under Constant Current And Temperature Stress
30、 JESD201 Environmental Acceptance Requirements For Tin Whisker Susceptibility Of Tin And Tin Alloy Surface Finished JESD22-A121 Measuring Whisker Growth On Tin And Tin Alloy Surface Finishes JP002 Current Tin Whiskers Theory And Mitigation Practices Guideline J-STD-001 Requirements for Soldered Elec
31、trical and Electronic Assemblies J-STD-002 Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires J-STD-005 Requirements for Soldering Pastes J-STD-075 Classification of Non-IC Electronic Components for Assembly Processes TECHAMERICA GEIA-GEB-0002 Reducing the Risk of Tin W
32、hisker-Induced Failures in Electronic Equipment TECHAMERICA GEIA-HB-0005-1 Program Management/Systems Engineering Guidelines For Managing The Transition To Lead-Free Electronics TECHAMERICA GEIA-HB-0005-2 Reducing the Risk of Tin Whisker-Induced Failures in Electronic Equipment TECHAMERICA GEIA-HB-0
33、005-3 Rework/Repair Handbook to Address the Implications of Lead-Free Electronics and Mixed Assemblies in Aerospace and High Performance Electronic Systems TECHAMERICA GEIA-STD-0005-1 Performance Standard for Aerospace and High Performance Electronic Systems Containing Lead-free Solder TECHAMERICA G
34、EIA-STD-0005-2 Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems TECHAMERICA GEIA-STD-0005-3 Performance Testing for Aerospace and High Performance Electronic Interconnects Containing Pb-free Solder and Finishes TECHAMERICA GEIA-STD-0006 Require
35、ments for Using Solder Dip to Replace the Finish on Electronic Piece Parts JEDEC Publication No. 70C Page 13 Annex A (informative) Standards The standards referenced in this document are in alpha-numeric order with a brief description. They are grouped by the currently maintaining body and do not in
36、clude revision numbers. Documents beginning with JEP, J-STD, JESD, JS, JEDEC-EIA are JEDEC or joint JEDEC documents. AEC - Q100 Stress Qualification For Integrated Circuits: This document contains a set of failure mechanism based stress tests and defines the minimum stress test driven qualification
37、requirements and references test conditions for qualification of integrated circuits (ICs). These tests are capable of stimulating and precipitating semiconductor device and package failures. The objective is to precipitate failures in an accelerated manner compared to use conditions. AEC - Q100-001
38、 Wire Bond Shear Test: This test establishes a procedure for determining the strength of the interface between a gold ball bond and a package bonding surface, or an aluminum wedge/stitch bond and a package bonding surface, on either pre-encapsulation or post-encapsulation devices. This strength meas
39、urement is extremely important in determining two features: 1) the integrity of the metallurgical bond which has been formed. 2) the reliability of gold and aluminum wire bonds to die or package bonding surfaces. AEC - Q100-002 Human Body Model (HBM) Electrostatic Discharge Test: The purpose of this
40、 specification is to establish a reliable and repeatable procedure for determining the HBM ESD sensitivity for electronic devices. AEC - Q100-004 IC Latch-Up Test: The purpose of this specification is to establish a reliable and repeatable procedure for performing an IC Latch-Up Test. AEC - Q100-005
41、 Non-Volatile Memory Program/Erase Endurance, Data Retention, and Operational Life Test: This test is intended to evaluate the ability of the memory array of a standalone Non-volatile Memory (NVM) integrated circuit or an integrated circuit with a Non-volatile Memory module (such as a microprocessor
42、 Flash Memory) to: sustain repeated data changes without failure (Program/Erase Endurance), retain data for the expected life of the Non-volatile Memory (Data Retention), and withstand constant temperature with an electrical bias applied (Operating Life). AEC - Q100-006 Electro-Thermally Induced Par
43、asitic Gate Leakage Test (GL): The purpose of this specification is to establish a reliable and repeatable procedure for determining surface mount integrated circuit susceptibility to Electro-Thermally Induced Parasitic Gate Leakage (GL). This specification may also be used as an evaluation tool for
44、 determining the susceptibility of circuit designs, molding compounds, fabrication processes, and post mold cure processes to GL. JEDEC Publication No. 70C Page 14 Annex A (informative) Standards (contd) AEC - Q100-007 Fault Simulation and Test Grading: This test method defines fault grading procedu
45、re and specifies a level to which the manufacturing test program for the device under test must detect faults. Parametric failures are not covered. Another term for fault grading is fault simulation. Fault grading applies to all digital circuits including the digital portion of mixed signal and line
46、ar circuits. Fault grading does not apply to the linear portion of the circuits. Also, this document covers modeling and logic simulation requirements; the assumed fault model and fault simulation requirements; and the procedure that must be followed to evaluate and report test coverage. AEC - Q100-
47、008 Early Life Failure Rate (ELFR): This test method is applicable to all IC part qualifications. In the case of many parts, generic data (see Q100, section 2.3) may fulfill the requirements of this test method. If the supplier is qualifying a part for which no generic data is available (unproven te
48、chnology or design rules) for general usage then the requirements of this test method should be utilized to meet the requirements of Q100. AEC - Q100-009 Electrical Distribution Assessment: This specification describes test methods for assessing electrical parameter characterization, distributions (
49、e.g., to AC, DC and timing, etc.) and parametric shifts of integrated circuits which have established supplier datasheet limits. For new parts, these datasheet limits are determined through application of the Characterization procedure AEC-Q003 as referenced in the AEC-Q100. The results are used to determine the capability to meet the performance requirements of the device specification. The results can also be used to set device test limits (e.g., LTL and UTL). AEC - Q100-010 Solder Ball Shear Test: The purpose of this test method is to define the procedure for measuring th
