1、In I Co r n w 7 JEDEC STANDARD F _/- . Design for Testability Guidelines JEDEC Standard No. 12-5 (Addondurn No. 5 to JEDEC Standard No. 12) AUGUST 1988 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT ?I -l NOTICE JEDEC Standards and Publications contain material that has been prepared, prog
2、ressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating inte
3、r- changeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products no
4、t conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. JEDEC Standards or Publications are adopted without regard to whether or not their adoptio
5、n may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represe
6、nts a sound approach to product specification and application, principally from .the solid state device manufacturer viewpoint. Within the JEDEC organization there. are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately become an EIA Standard. Inquiries, comme
7、nts, and suggestions relative to the content of this JEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Eye.Street, N.W., washington, D.C. 20006. -1 COPYRIGHT 1988 ELECTRONIC INDUSTRIES ASSOCIATION Published by ELECTRONIC INDUSTRIES ASSOCIATI
8、ON Engineering Department . 2001 Eye Street, N.W. Washington, D.C. 20006 PRICE: $30.00 :n U.S.A. C3*:-4-.-I EIA JESDLZ-5 88 m 3234600 0004873 2 m Design For Testability Guidelines . Prepared by: JEDEC Committee on Semicuctom Integrated Circuits i a EIA JESDL2-5 88 m 3234600 O004874 4 m 1. 2. 3. 4 5.
9、 6. - I. 8. JEDEC Standard No. 12-5 DESIGN FOR TESTABILITY GUIDELINES TABLE OF CONTENTS Introduction Terms and Definitions Structured and Non-structured Approaches to Designing For Testability Isolation Techniques fol: Megacell/Memory/Analog Structures in Semicustom ICs to Enhance Testability Automa
10、tic Test Vector Generation Techniques Test Program Generation From Simulation Files Enhancing DC Parametric and Board Level Testing Summary and Conclusions Appendix A Bibliography of Published Literature NOTE: Two chapters are in the process of completion and Packaging Impact on Design For Testabili
11、ty will be included in a future edition: 1) 2) Fault Detection, Fault Coverage, Fault Simulation and TestabilityAnalysis ii EIA JESD12-5 88 m 3234600 0004875 b m 5 JEDEC Standard No. 12-5 Page 1 DESIGN FOR TESTABILITY GUIDELINES CHAPTER 1 INTRODUCTION (From JEDEC Council Ballot JCB-87-46, formulated
12、 under the cognizance of JC44 Committee on Semicustom Integrated Circuits.) The concern most often voiced by Application Specific integrated Circuit (ASIC) users is that of testability. Many vendors have taken steps to try to minimize the concerns of their customers but, to date, each company has in
13、stituted its own policies and the customers have seen little to ease their confusion. This document is composed of inputs from many IC manufacturers and some IC users. It is intended to bring together a coherent approach to dcsigriing for testability. It is not intended as a specification, nor is it
14、 to be interpreted as the only way to design. It should, rather, be used as guidance (as . the title implies) when designs are being initiated. As the reader progresses through this guide he will notice that there is no list of authors and no company labels are shown. This -was not done to slight th
15、e authors or minimize the contributions that they and their companies made, It was done, instead, to try to emphasize the broad base of contributors and companies who support these guidelines. The second section of this guide contains definitions for most of the terms commonly used with reference to
16、 designing for testability. These definitions are the result of industry-wide discussion and, as such, represent the consensus of the industry. several topics will- he covered. Perhaps the item that leads to the most discussion is Fault Simulation. This technique enables design engineers to evaluate
17、 their test patterns (input stimulus and expected output values) to determine whether these patterns will detect faults (errors in the circuitry) that may occur during either the design or processing stages. A fault simulator uses fault models, such as a node shorted to power (stuck-at-one) or a nod
18、e shorted to ground (stuck-at-zero), and compares the response of a fault-free circuit with the response of a faulty circuit after applying test patterns supplied by the design engineer. if the response of the fault-free circuit is different than the response of the faulty circuit, then the test pat
19、terns have detected the fault. By faulting all the nodes in the circuit, the fault simulator will produce the test pattern fault coverage (the percentage of faults detected vs. total faults tested). The higher the fault coverage, the better the I - I EIA JESDL2-5 88 m 3234600 0004876 8 m ! L JEDEC S
20、tandard No. 12-5 Page 2 DESIGN FOR TESTABILITY GUIDELINES test pattern will separate a faulty circuit from a fault-free circuit. BY analyzing which faults have not been detected by the current set of test patterns, additional test patterns can be generated by the design engineers in order to detect
21、the faults which were missed. Many vendors recommend greater than 90 percent fault coverage, Designing testability into any circuit will affect the hardware to some degree. Additional Logic will most probably have to be included for any of the methods outlined in this guide. This additional logic wi
22、ll increase the amount of silicon required to implement the design and therefore increase the cost. The savings from enhanced testability do not usually show up until the testing cost of the part and its end system are analyzed. These costs include the-labor required to generate the test vectors, th
23、e computer time to evaluate the vectors, and the actual time required to test the part. Depending on how the additional circuitry is implemented, the ac performance of the part may be degraded. Each of these factors will also be discussed. The final section of this guide is a bibliography of documen
24、ts that the reader may want to investigate. While this List is extensive, it is by no means all-inclusive. The reader is encouraged to do some follow-up investigation after finishing this document. -3 -i EIA JESDL2-5.88 I 3234600 0004877 T JEDEC Standard No. 12-5 Page 3 DESIGN-FOR TESTABILITY GUIDEL
25、INES CHAPTER 2 TERMS AND DEFINITIONS 1, Node: The end-point or more branches meet. of a branch in a network or a point at which two 2. Fau1.t: A defect that may cause a failure in the circuit operation and/or timing. NOTE : Subclassifications of faults may not be mutually exclusive. 2.1 Parametric F
26、ault: A fault in a circuit that causes failure to meet ac or dc specifications but does not cause functional failure. 2.2 Functional Fault: A fault that causes improper logical operation of a circuit. 2.2.1 Combinational Fault: A functional fault that is not affected by the sequence input stimuli. o
27、f the 2.2.2 Sequential Fault: A functional fault that is affected by the sequence of the input stimuli. 3. -Stuck-ak-O Fault: A fault in a digital circuit characterized by a node remaining at a logic low (O) state regardless of changes in input stimuli. 3.1 Stuck-at-1 Fault: A fault in a digital cir
28、cuit characterized by a node remaining at a logic high (1) state regardless of changes in input stimuli. EIA JESDI2-5 88 W 3234600 0004878 I W 1 JEDEC Standard No. 12-5 Page 4 DESIGN FOR TESTABILITY GUIDELINES 4. Short Circuit Fault: A fault in a circuit that alters the number of nodes by connecting
29、 two or more nodes together. 4.1 Open Circuit Fault: 1 A fault in a circuit that alters the number of nodes by breaking a node into two or more nodes. 5. Test Vector: A single instance of input stimuli and expected output responses. 6. Test Pattern: A set of test vectors. 7. Test Program: A test pat
30、tern and instructions suitable for use on Automatic Test Equipment. A test program may be used to perform functional and parametric (ac, dc, or other). tests, Note: 8. Detectable Fault: A functional fault for which a test patterncan be created that will always cause the effects of the fault to be ob
31、servable at an externally accessible node. 8.1 Detected Fault: A functional fault that causes effects that are observed at an externally accessible node when the circuit is exercised by the existing test pattern. 8.2 Undetected Fault: A functional fault that causes effects that are not observed at a
32、n externally accessible node when the circuit is exercised by the existing test pattern. 5. -I EIA JESDL2-5 88 W 3234600 0004879 3 I JEDEC Standard No. 12-5 Page 5 DESIGN POR TESTABILITY GUIDELINES O 9. Undetectable Fault: A functional fault for which no test pattern can be created that will cause t
33、he effects of the fault to be observable at an externally accessible node. 10. Test-Pattern Fault Coverage: The ratio of the total number of detected faults to the total number of detectable faults. 11. Fault detectability Ratio: The ratio of detectable faults to the sum of detectable and undetectab
34、le faults. 12. .Fault Grading: The process of determining the test-pattern fault coverage of a circuit. 13. Fault-Tolerant Design: A design approach to enhance the ability of a circuit to remain operational after the occurrence of a fault. Note: * Fault-tolerant design techniques may impact fault de
35、tection. 14. Controllability: The ability of a node to be established at specific logic statets) by applying stimuli to the circuits externally accessible node(s). 15. Observability: The ability to determine the logic state(s) of a node at the circuits externally accessible node(s). is. Circuit init
36、ialization: A sequence of stimuli that set internal nodes of a circuit to a predictable state. JEDEC Standard No. 12-5 Page 6 DESIGN FOR TESTABILITY GUIDELINES (Intentionally left blank) a JEDEC Standard No. 12-5 Page 7 DESIGN FOR TESTABILITY GUIDELINES CHAPTER 3 STRUCTURED AND NON-STRUCTURED APPROA
37、CHES TO DESIGNING FOR TESTABILITY Design For Testability (DFT) refers to a design approach that enables thorough testing of a system with minimal effort and maximum covera.ge. A circuit is termed testable when the testing effort involved is minimal compared to the design and manufacturing efforts. T
38、he key concepts in DFT are controllability and observability. (See definitions in Chapter 2.) The purpose of the various DFT techniques is to increase the ability to control/observe internal nodes from external inputs/outputs. Some states of a circuit are buried in logic and cannot easily be control
39、led or observed by external pins. This makes the generation of test vectors more time consuming and usually results in more test vectors being generated. This problem can be addressed by adding special test pins that increase the conkroilability or observability of these states. If extra pins are no
40、t available, on-chip test logic can be used to test portions of the circuit while it is operating in a test mode. Input combinations that cannot occur during the normal operation of the circuit can be used to place the circuit in the test mode. On-chip test circuitry can also be used to partition th
41、e circuit into logical subsystems that can be tested in parallel. Testing smaller logical subsystems simplifies the task of test vector generation. Because the logical subsystems operate in parallel, these test vectors may be merged together, resulting in reduced test time on the tester. TQ help sol
42、ve the testing problem there are two basic approaches prevalent in the industry. The first approach is categorized as ad hoc or nonstructured and the second approach is categorized as a structured approach. The nonstructured techniques are the ones that can be applied to a given product, biitare not
43、 directed at solving the general problem of testing sequential logic. Non-structured techniques usually provide specific solutions at lower cost than structured approaches would, but without the general applicability. The structured techniques tend to solve the general problem with design methodolog
44、y and lend themselves more easily to design automation. The implementation of a structured approach to DFT begins with the design process. Most structured techniques rely on the “shift register:“ method which connects all memory elements (latches, I EIA JESDL2-5 88 m 3234b00 0004882 3 m JEDEC Standa
45、rd No. 12-5 Page 8 DESIGN FOR TESTABILITY GUIDELINES flip-flops) into a shift register and uses each element as pseudo-nput/output for testing purposes. Converting sequential logic into combinational circuits smplifies test pattern generation and reduces test development costs. There are a number of
46、 DFT techniques used by VLCI chip designers; three are briefly discussed below. ISOLATION OF FUNCTIONAL BLOCKS One of the simplest methods of designing testability into a circuit is to partition the functional blocks such that each may be individually tested as a separate unit. In an integrated circ
47、uit, only the nodes at the external pins can be controlled and observed directly. In order to isolate the functional blocks of the chip, internal nodes must be made controllable and observable from the external pins. . Additional logic such as multiplexers may have to fie added to perform this funct
48、ion. This, in turn, will increase gate count. If the design is implemented in gate arrays, enough extra logic may be required as to force the use of the next larger array. In cell based designs, each added gate will increase die size. The total number of internal signals that must be isolated will d
49、ictate the exact amount of additional logic that will have to be added. If extra package pins are available, internal signals may be brought directly to the outside world for observation at no additional cost. If package pins are not available, however, bringing internal signals out will force the use of a larger package. Costs will vary with the package selection. Any added logic will- have an effect on the ac performance of the circuit. If the added logic is to be placed in a critical timing path, a trade off will result between performance and testability. J EIA J
