1、STANDARD SPECIFICATION FOR DESCRIPTION OF “6“ SERIES CMOS DEVICES MAY 1980 - (Revision of JEDEC Tentative Standard No. 13-A) PRICE: $12.00 FORMULATED BY JEDEC SOLID STATE PRODUCTS COUNCIL JEDEC STANDARD NO. 13-6 NOTICE This JEDEC Standard contains material which has been prepared and progress- ively
2、 reviewed and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel, JEDEC Standards are designed to serve. the public interest through eliminating misunderstandings bet ween manufacturers and purchasers, faci I i tat ing inter- changeability and
3、improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or non-member of JEDEC from manufacturing or selling products not conforming to such
4、 standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. Recommended standards are adopted by JEDEC without regard to whether or not their adoption may involve patents
5、 or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any ob1 igation whateveteto parties adopting the recommended standards. This information included in JEDEC Standards represents a sound approach to product specification
6、and appl ication, principally from the sold state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard may be further processed and ultimately become an EIA Standard. Inquiries, commentis, and suggestions relative to the content of this JEDEC Sta
7、ndard should be addressed to the JEDEC Executive Secretary at the EIA Headquarters, JEDEC Electronic Indust ries Association 2001 Eye Street N.W. Washington, D.C. 20006 - - - _- . EIA JESDL3-B 80 m 3234600 0004957 8 m O O STANDARD SPECIFICATION FOR DESCRIPTION OF llB1l SERIES CMOS DEVICES TABLE OF C
8、ONTENTS Paragraph 1.0 Purpose and Scope 2.0 Definitions 3.0 Standard Specification TABLE 1 TABLES 2 - 24 JEDEC Standard No. 13-8 Paqe 1 2 5-6 7-41 . EIA JESDL3-B 80 W 3234600 0004958 T W JEDEC Page 1 * Standard No. 13-6 * STANDARD SPECIFICATION FOR DESCRIPTION OF “B“ SERIES CMOS DEVICES (From JEDEC
9、Council Ballot JCB-80-6, formulated under the cognizance of JEDEC Subcommittee JC-40.2 on CMOS Standardization.) 1.0 PURPOSE AND SCOPE 1.1 Purpose To develop a standard of “BI1 Series CMOS Specification to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device
10、specif ication and system design by users. 1.2 Scope This Tentative Standard covers standard specifications for description of W1I Series CMOS Devices. O 2.0 DEFINITIONS 2.1 “Btl Series “B“ Series CMOS includes both buffered and unbuffered devices. 2.2 Buffered A buffered device output is one that h
11、as the characteristic. that the output llonll impedance is independent of any and all valid input logic conditions, both preceding and present. Unbuffered - see paragraph 3.4 for definition. 2.3 I EIA JESDL3-B 0 3234b00 0004959 L = JEDEC Standard No. 13-6 Page 2 3.0 STANDARD SPECIFICATION 3.1 Listin
12、g of Standard Specifications 3.1.1 Table 1 lists the standard dc specifications for “6“ Series CMOS devices. 3.1.1.1 Table 24 lists the IOL and IOH standard .specification specifically for the 4049U6 and 40506 types. For IDD, use same specification as for Buffers/Flip Flops in Table 1; also VOH, VOL
13、, VIH, VIL, and IIN are the sameas in Table 1. 3.1.2 Analog Switch Standard 3.1.2.1 Table 2 lists dc standard specifications specifically for the 40166 type. For IDD, use same specification as for Gates in Table 1; also II and Ci are the same as in Table 1. . 3.1.2.2 Table 3 lists dc standard specif
14、ications specifically for the 40666 type. For IDD, use same specification as for Gates in Table 1; also II and Ci are the same as in Table 1. 3.1.2.3 Standardized test conditions for additional analog-switch . parameters are listed in Table 4. AC Standards - see paragraph 3.1.3. 3.1.2.4 3.1.3 AC Sta
15、ndard Specifications 3.1.3.1 AC (Dynamic) Parameter Standard Test Methods and Defi- ni tions Figure 1 - Figures 2-5 - Waveform Definitions Table 5 - List of Dynamic Electrical Characteristics. Test Configuration and Conditions 3.1.3.2 Standard ac Parameter Limits Table 6 - Buffered Gates Table 7 - U
16、nbuffered Gates Table 8 - Flip Flops (40136 and 40276) Table 9 - Analog Switch (40166) Table 10- Analog Switch (40668) Table 11- Exclusive OR/NOR Gates (40706 and 40776) Table 12- And-OR Invert Gates (40858) and (40866) EIA JESDl3-B 0 = 3234600 0004760 8 = JEDEC Standard No. 13-8 Page 3 3.1.3.2 Stan
17、dard ac Parameter Limits (continued) Table 13- Table 14- Table 15- . Table 16- Table 17- Table 18- Table 19- Table 20- Table 21- Table 22- Table 23- 40768 45148 and 45158 45328 45558 and 45568 401748 and 401758 40998, 47238 and 47248 45088 4049UB 40508 4510B, 45168 45188, 45208. 3,2 Absolute Maximum
18、 Ratings In the maximum ratings listed below, voltages are referenced to Vss. ABSOLUTE MAXIMUM RATINGS DC Supply Voltage VDD -0.5 to +18 V Input Voltage DC Input Current VI -0.5 to VDD -I- 0.5 V II - +10 mA Storage Temperature Range TSTG -65 to +150 OC 3.3 Recommended Operating Conditions Recommende
19、d operating voltages are listed below. RECOMMENDED OPERATING CONDITIONS DC Supply Voltage VDD +3 to +15 V Operating Ambient TA Temperature Range Military -Range Devices -55 to +175 OC Commercial-Range Devices -40 to +85 OC EIA JESDL3-B BO = 3234600 00049bl T = c JEDEC Standard No, 1343 Page 4 I. 3.4
20、 Designation of irBic Series CMO.5 Devices Those parts which! have analog inputs and/or outputs shall be included in the Wtl Series providing those parts maximum ratings and logical input and output pararnet.ers conform ta the iBii Series, such as (including, butnot limited to): 40466 . Devices with
21、 Bipolar Outputs I Analog Switches Analog Multiplexers. Monostable and Astable Multivibrators Schmitt Triggers Products that meet ii3ii Series specifications except that the logical outputs are not buffered and the VIL and VIH specifications differ from iiBii Series as shown in Table 1: shall be mar
22、ked with, the _. UB designation, such as (including, but not limited to): 4000UB 4001UB 4002UB 4007UB 4009UB 4011UB 4012UB 4023UB 4025UB 4041UB 4049UB 4069UB 4441UB 4449UB 4501UB 457.2UB EIA JESDL3-B 0 3234b00 00049b2 L JEDEC Standard No. 13-8 Page 5 ? rim* q .?Z mo VIOC rim rimu 9 ?Y FI “ * i-: ? F
23、IOU 9 ?“! 4“ “! 99 99. i m-2 lu*: I ? ?C moo ooc dN N*O: z ? rimu 9 9“) rl“ I I “! 39 99. 7 2 i= a !=! k k n a a O Cl W o U d r2 Z I- Ln I U W J m 2 x ZR s sl mom mou -4 mom mou rlr Ji- - w E- IPROBLEM HARD COPY .o : EIA JESDL3-B 80 m 3234600 0004963 3 m JEDEC Standard No. 13-8 Page 6 73 ? ii 73 ? 1
24、79 oohl Iw OON W *In. 304 O04 ? ? III i: I I c tD n f U .rl 5 e 4 n LI O Yi U Ln N 4 + )i U a / - I EIA JESDL3-B 0 W 3234600 0004766 7 W + JEDEC +Y Standard No. 13-6 Page 9 =. :* c c ?ZZ O00 O m2: m o oc o NO N mm m III I I .I “199 mr-rl rl I II III 999 r“ oog 5:ZN N o O0 N 5: %Fi III III ? mr-rl rl
25、 III I II III t 999 I-“ O00 8ZN N O0 rl UN N 8 mm III III 499 mbrl H I l 8 m PI rl El n O U 5 L O o=- ln l-t L O c rn mom HH U U B rl ci U u k u cl P u Le H 3- rn W U JEDEC EIA JESDL3-B 0 M 3234600 0004767 O Standard No. 13-6 Page 10 SWITCH OPUT TABLE 3A 40668 SWITCH TEST CONDITIONS FOR VIHC , I . E
26、IA JESDL3-B 80 3234b00 00049b8 2 m PARAMETER Total Harmonic Dis tort ion Cutoff Frequency -50 dB Feedthrough Frequen (Switch Off) -50 dB Crosstalk Frequen 4 Switches) (Between any 2 of TEST CONDITIONS vc = VDD = +5v vss - -5v V,(pp) = 5V Sine Wave centered on O Volts 5, = 10k n Fis = 1 kHz Sine Wave
27、 vc - VDD - +5v vss = -5v Sine Wave centered on O Volts 5, =kn 20 Loglo OS O (frnax) vos ia p4 = -3db VDD = +5v vc = vss = -5v % =fin VIs(pp) - 5V Sine Wave centered on O Volts VIsipp)(A) - 5V Sine Wave centered on O Volts R = 1kG L Source Impedance to inouts of both switches = 50D I TABLE 4 STANDAR
28、D TEST CONDITIONS JEDEC Standard No. 13-8 Page 11 UNIT MHz (min) MHz (min) MHz (min) For ac characteristics for 40168 and 40668 JEDEC Standard No. 13-8 i Page 12 PARAMETER Switch Capacitance Input, Cis , output, cos Feedthrough, Cios Crosstalk peak-to- peak voltage (Control Input to Signal Output) C
29、ontrol Input Repetition Rate I EIA JESDL3-B 80 = 3234b00 0004769 4 TEST CONDITIONS VDD = t5v Pss = vc -. -5v Bridge Meas. 100 Wz or 1 MHZ, VIS - -5v VDD = 1ov vss - 0v tr. tf - 20 ns vC = 1OV Square Wave % - 10kn VDD - 1ov vss = ov IS DD vos = 112 vos 1 kHz Vc tr, tf - 20 ns = Square Wave (O to 1OV)
30、 % CL - 50 pF TABLE 4 STANDARD TEST CONDITIONS For ac characteristics for 40168 and 40668 (can tinued) UNIT , mV (ma4 a O . . . .- - _. - EIA JESDL3-B 0 m 3234600 0004970 O m JEDEC Standard No. 13-8 Page 13 DUT N Inputr . 4 ? 3 c K outputs “SS Notes - i) Parameters specified at TA=25eC. VDD=5V, 1OV
31、15V 2) Each output loaded with 50pF 6 200k i2 3) Input t.= . .% t.p =20ns FIGURE 1 . STANDARD ac TEST CONFIGURATION AND CONDITIONS EIA JESD33-B 80 W 3234b00 0004973 2 = 3EDEC Standard No. 13-i3 Page 14 t I N EIA JESDL3-B BO m 3234600 0004972 4 JEDEC Standard No. 13-6 Page 15 - - -50% - c_- - - - 40%
32、 yss - - L. - - - 5 O% - OUTPUT *(LH) OR (HL) OPTIONAL “DD Preset “ss Set, Reset, or EIA JESDL3-B 80 3234600 0004973 b I JEDEC Standard No. 13-6 Page 16 l n c2 5. I- in W I- ol) -1 VL E O Cu _L W z in W e I I- kn c O i c? U m I O -II O0 wl n in in f C EIA JESDL3-B 80 m 3234600 0004974 8 m - x -I I a
33、. U - x i - JEDEC Standard No. 13-8 Page 17 X ww VIU = ma UC c, O tic c, VI*- m3 I cw uu U aJL U vu Em c w .C u0 3c i mm no tu ? 2sn h N EIA JESDL3-B 80 m 3234600 0004975 T m JEDEC Standard No. 13-8 Page 18 r PARAMETER I Output Transition Time t, (All Buffered Bates) I tTHL i I I I Propagation Delay
34、 Time t, 110OOR ,400 B, 4002q 401 1 B, 401 24 40234 PHL 40258, 40718, 43728, 40733, 4079, 40818, 40826 I I “DD I 5 10 15 5 10 15 5 10 15 MAX. LIMIT 200 1 O0 ao 300 130 1 O0 350 150 110 TABLE 6 BUFFERED GATE ac LIMITS UNIT i EIA JESDL3-B 80 3234b00 0004976 1 JEDEC Standard No. 13-B Page 19 PARAMETER
35、Output Transition Time 4000U6, 4001 UB, 4002UB y 401 1 U6 y 401 2UB 4023118, 4r)25UB, 4007UB, 4069UB 4000U6, 4001U6, 4002UBy 40 IUB, 4012UB 4023116 , 4025UB 4007U6, 4069UB Propaaation Delay Time 4000U6, 4001 U6 , 4OO2U6, 401 1 UB 4023118, 4025UB 401 2UB 4007UB y 4069UB 5 10 15 5 10 15 5 10 15 5 10 1
36、5 5 10 15 MAX. LIMITS 200 1 O0 80 360 180 130 200 1 O0 80 180 1 O0 80 125 75 55 TABLE 7 UNBUFFERED GATE ac LIMITS UNIT ns ns ns ns ns EIA JESDL3-B 80 M 3234600 0004977 3 = JEDEC Standard No. 13-8 Page 20 - PARAMETER Output Transition Time . _. . .,. . - . -. -.-. Propagation Delay Time: Clock to Q o
37、r h Set to Q, Reset to 4 Reset to Q, Set to Max. Clock Input Frequency Min. Clock Pulse Width Min. Set or Reset Pulse Width 5 10 15 4 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 LI! MIN. i .5 4.0 5.0 S MAX. 200 1 O0 80 360 180 130 350 160 120 450 ?O0 150 330 120 1 O0 250 1 O0 70 UNIT I , YH z ns
38、 ns TABLE 8 FLIP-FLOP (40136 and 40278) ac LIMITS PROBLEM HARD COPY . EIA JESDL3-B 0 = 3234600 0004978 5 ;su t,CL PARAMETER Min. Data Setup Time: 401 3B 40278 Clock Input Rise or Fall Time Min. Set & Reset Removal Time Min. Data Hold Time TABLE 8 “DO o 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 FLIP-FL
39、OP ac LIMITS (continued) - I - - JEDEC Standard No. 13-8 Page 21 LI MIN. rs MAX. 60 30 25 250 1 O0 80 15 4 1 60 30 25 UNIT 1 ns EIA JESDL3-B 0 M 3234b00 0004979 7 M 5 10 JEDEC Standard No. 13-6 RL=l ka See Fig. 5 Page 22 5 10 15 . PARAMETFR RL =lk n See Fig. 5 Propagation Delay Time (Signal In to Si
40、gnal- Out) Propagation Delay Time (Control Turn On To Signal Out) Propagation Delay Time (Control Turn off to high impedance state) vc “DD See Fig. 1 and 2 5 15 1 l5 1 I TABLE 9 ANALOG SWITCH (40166) ac LIMITS MAX. LIMIT 1 O0 50 40 90 45 35 160 160 160 UNIT ns ns ns EIA JESDl3-B 80 3234600 0004780 3
41、 = “OD (V) t, t MAX. CONDITIONS LIMIT tPZH, tPZL 5 10 tPHZ, tPLZ “c = “O0 See Fig. 1 and 2 PARAMETER Propagation Delay Time (Signal In to Signal Out) Propagati on Delay Time (Control Turn On To Signal Out) Propagation Time (Control turn-off ta high impedance state) JEDEC Standard No. 13-8 Page 23 .
42、._ 1 O0 50 15 I I 40 TABLE 10 ANALOG SWITCH (40668) ac LIMITS UNIT ns ns ns EIA JESD13-B 80 I 3234600 0004981 5 I- . JEDEC Standard No. 13-E Page24 ( ?SOC 1 MAX. LIMIT SYMBOL UNIT MIN. t, t Output Transi tion Time . _ - - 200 ns . ._ 5 - 10- 15 - - loo.- 80 Propagation Delay Time t, t 300 130 1 O0 n
43、s 5 10 15 TABLE 11 ac LIMITS FOR 40708 and 40778- ELA JESDL3-B 80 m 3234600 0004982 7 m JEDEC Standard No. 13-6 Page 25 SYMBOL t, t t t t PARAMETER Output Trans i ti on Time Propa ation Delay Time ?Data) Propagation Delay Time (Data) Propa ation Delay . Time ?Inhibit) Propa ation Delay Time Qinhibi
44、t) 5 10 15 5 10 15 5 10 15 t L TABLE 12 ac LIMITS FOR 40858 and 40866 5 10 15 5 10 15 LIMIT MIN. 5OC) MAX. 200 1 O0 80 620 250 180 450 180 130 500 200 140 300 120 80 IINTT ns ns ns ns ns EIA JESDL3-B 80 m 323YbOO OOOY783 7 m Page 26 (25OC) MAX. 360 180 130 200 1 O0 80 LIMIT MIN. SY#BOL PARAMETER UNI
45、T ns %LH Output Transition Time 5 10 15 ns 5 10 15 Output Transition Time . 5 10 15 600 250 180 Propagation Delay Time ns ns ns MHz ns ns LIS C to Q, R to Q tPHZ tPLZ 5 10 15 340 150 120 Three-State Disable Delay Time Turn Off tPZH, tPZL 5 10 15 400 160 120 Three-State Disable Delay Time Turn On 1.8
46、 4.5 6.0 Clock Input Frequency 5 10 15 fCL 5 10 15 Clock Pulse Width 260 110 80 370 150 110 twL I t“ 5 10 15 5 10 15 twH Reset Pulse Width trCL, tfCL Clock Input Rise and Fall Time 10 4 TABLE 13 ac LIMITS FOR 40768 ,- EIA JESDL3-B 80 m 3234b00 0004984 O m JEDEC -Standard No. 13-6 Page 27 TABLE 13 ac LIMITS FOR 40768 (continued)
