1、JEDEC STANDARD Two-Resistor Compact Thermal Model Guideline JESD15-3 JULY 2008 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and app
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9、produce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10thStreet Suite 240 South Arlington, Virginia 22201-2107 or call (703) 907-7559 JEDEC Standard No. 15-3 -i- TWO-RESISTOR COMPACT THERMAL MODEL
10、GUIDELINE Contents 1 Scope 1 2 Normative references 1 3 Definition of the two-resistor compact thermal model 2 3.1 Overview 2 3.2 General criteria for compact thermal models 2 3.3 The two-resistor methodology 2 3.4 Network model definition 3 4 Determination of the metrics 4 4.1 Junction-to-board the
11、rmal resistance (JB) 4 4.2 Junction-to-case thermal resistance (JCtop5 Alternative metrics 5 6 Application Considerations 5 6.1 Overview 5 6.2 Network calculator/spreadsheet-based tools 5 6.3 Three-dimensional modeling and simulation tools 7 6.3.1 Overview 7 6.3.2 Conduction-focused tools 8 6.3.3 Co
12、mputational fluid dynamics (CFD) tools 8 6.3.4 Representing a two-resistor model in 3D space 9 6.3.4.1 Block-and-plate method 10 6.3.4.2 Block-and-surface resistance method 11 6.3.4.3 Network object method 11 6.4 Accuracy bounds of a two-resistor model 12 7 Methodology for constructing and using two
13、-resistor model 12 7.1 Two-resistor model construction and usage 12 7.2 Example illustrating the use of a two-resistor model 13 8 Bibliography 14 JEDEC Standard No. 15-3 -ii- TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE Contents (continued) Figures 1 Two-resistor model network 3 2 Package on PCB 6 3
14、 Equivalent thermal resistance diagram of two-resistor model on PCB 6 4 Thermal resistance diagram of system with known board temperature 6 5 Two-resistor model in conduction-only simulation environment 8 6 Two-resistor model in CFD simulation environment 9 7 Two-resistor model represented in 3D spa
15、ce using a block-and-plate approach 10 8 Two-resistor model represented using a block-and-surface resistance approach 11 9 Two-resistor model as a three-dimensional network object 11 10 Thermal resistance diagram for worked example 13 Tables 1 Typical cooling regimes in electronics 7 JEDEC Standard
16、No. 15-3 Page 1 TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE (From JEDEC Board Ballot JCB-08-29, formulated under the cognizance of the JC15.1 Committee on Thermal Characterization.) 1 Scope This document specifies the definition and construction of a two-resistor compact thermal model (CTM) from th
17、e JEDEC junction-to-case and junction-to-board thermal metrics. The guidance provided in this document only applies to thermal metrics defined in JEDEC standards JESD51-8 and JESD51-12. The scope of this document is limited to single-die packages that can be effectively represented by a single junct
18、ion temperature. 2 Normative references 1. JESD51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device), Dec. 1995. 2. JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air), Dec. 1995. 3. JESD51-3, Low Effecti
19、ve Thermal Conductivity Test Board for Leaded Surface Mount Packages, Aug. 1996. 4. JESD51-5, Extension of Thermal Test Board Standards For Packages With Direct Thermal Attachment Mechanisms, Feb. 1996. 5. JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection
20、(Moving Air), March 1999. 6. JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages, Feb. 1999. 7. JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions Junction-to-Board, Oct. 1999. 8. JESD51-9, Test Boards for Area Array Surface Mount Package
21、 Thermal Measurements, July 2000. 9. JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements, July 2000. 10. JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurement, June 2001. 11. JESD51-12, Guidelines for Reporting and Using Electronic Pa
22、ckage Thermal Information, May 2005. 12. JESD15, Thermal Modeling Overview 1). 13. JESD15-1, Compact Thermal Modeling Overview 1). 14. JESD15-2, Terms and Definitions for Modeling Standards 1). 15. JESD15-4, DELPHI Compact Thermal Model Guideline 1). 1)To be published. JEDEC Standard No. 15-3 Page 2
23、 3 Definition of the two-resistor compact thermal model 3.1 Overview Excluding the single-parameter metrics such as JA, the two-resistor compact model is the simplest and most intuitive of compact thermal models and occupies an important place in the spectrum of compact modeling methodologiesas stat
24、ed in JESD15-1. Although other compact model approaches(see JESD15-4) do exist that have a demonstrated higher accuracy, the simplicity and intuitiveness of a two-resistor model are attractive features. However, accuracy of such models remains a concern. Users should exercise care in using two-resis
25、tor model data for predicting package temperatures. The two-resistor model definition describes the thermal behavior of the chip package itself and its interconnection to the environment. The environmental conditions themselves are not a part of the model and must be specified by the user in terms o
26、f boundary conditions for the relevant application. 3.2 General Criteria for compact thermal models A compact thermal model should fulfil the following criteria. It should be of limited complexity. In todays technology, this equates to tens of nodes. It is conceivable that this number could increase
27、 over time with improvements in computer calculating power and the sophistication of CTM techniques. It should satisfy appropriate levels of boundary condition independence (BCI). BCI is a property of a CTM whereby it accurately calculates a chip temperature in a variety of application environments,
28、 which, in essence, impose different boundary conditions on the component. It is a goal of the CTM standardization effort that CTMs should demonstrate a high level of BCI. It should be vendor and software neutral. A CTM generation technique should be adaptable to standard conduction codes for perfor
29、ming a package-level thermal analysis. The CTM should be capable of insertion into standard numerical codes for system-level analysis. It should be fully documented and non-proprietary. 3.3 The two-resistor methodology The following are the key features of the two-resistor methodology. The compact m
30、odel is generated from JEDEC standard tests for junction-to-case resistance (JCtop) and junction-to-board resistance (JB). If measured values are not available, simulated values can be used (see 3.4). The starting point for the process is the availability of a part sample. The resulting compact mode
31、l contains artifacts from the test environments. An error estimate is not available during the model generation process. Like the other compact model approaches, the two-resistor compact model approach serves to mask data about the package that the supplier may regard as proprietary. JEDEC Standard
32、No. 15-3 Page 3 3 Definition of the two-resistor compact thermal model (contd) 3.4 Network model definition The JEDEC two-resistor model consists of three nodes as depicted in Figure 1. These are connected together by two thermal resistors which are the measured values of the junction-to-board (JB,
33、JEDEC Standard JESD51-8) and junction-to-case (JCtop, discussed in JEDEC Guideline JESD51-12) thermal resistances described above. For packages which are designed to inject heat directly on to the ground plane of the board, such as exposed pad packages, the user may consider replacing JBby JCbottom.
34、 If measured values are not available, simulated values of the junction-to-board and junction-to-case resistances can be used in constructing the two-resistor model, provided that the simulation approach has been validated to yield results equivalent to the measured results. Any simulated values mus
35、t be indicated as such. JCtopJBBoard NodeCase NodeJunction NodeFigure 1 Two-resistor model network The heating power, PH,is applied at the junction node. The board node is considered to be in direct thermal contact with the local environment immediately below the footprint of the package; normally t
36、he printed circuit board (PCB). The case node is considered to be in direct thermal contact with the local environment immediately above the top of the package (normally air, or a thermal interface material used in conjunction with a heat sink). Thus there are only two paths for the heat to leave th
37、e junction node and flow into the environment - through the case node and through the board node. The model does not account for heat flow through the sides of the package. JEDEC Standard No. 15-3 Page 4 4 Determination of the metrics 4.1 Junction-to-board thermal resistance (JB) This parameter is m
38、easured in a ring cold plate fixture (see JESD51-8). This test fixture is designed to ensure that all the heat generated in the package is conducted to the cold plate via the board. The metric is defined as: ( )HBJJBPTT /= where JB= thermal resistance from junction-to-board (C/W) TJ= junction temper
39、ature when the device has achieved steady-state after application of PH(C) TB= board temperature, measured at the mid point of the longest side of the package no more than 1mm from the edge of the package body (C) PH = heating power which produced the change in junction temperature (W) It is importa
40、nt to note that the JBmetric includes a contribution from the thermal resistance of the test board. Therefore, the thermal conductivity of the board affects the measurement results. The JESD51-8 standard requires that the metric be measured on a 2s2p board defined in JESD51-7, 9, 10, or 11. Measurem
41、ent of the board temperature very close to the edge of the package body is also intended to minimize the contribution from the board. Further details are available in JESD51-8. 4.2 Junction-to-case thermal resistance (JCtop) The metric is measured in a top cold plate fixture and is defined as: ( )HC
42、topJJCtopPTT /= where JCtop= thermal resistance from junction-to-case (C/W) TJ= junction temperature when the device has achieved steady-state after application of PH(C) TCtop= case temperature, measured at center of the package top surface (C) PH = heating power in the junction that causes the diff
43、erence between the junction temperature TJand the case temperature TCtop; this is equal to the power passing through the cold plate (W) The method employed to measure JCtopmust be reported2). The JESD51-12 standard provides a detailed discussion of the JCtop metric. 2)JEDEC Standard JESD51-13, which
44、 will define the method for measuring JCtop, is currently in preparation. JEDEC Standard No. 15-3 Page 5 5 Alternative metrics The two-resistor model guideline requires that the model be constructed from JBand JCtopas explained in this document. However, the question arises as to whether alternative
45、 metrics can be substituted in case either of these metrics are not available. Where a JBvalue is unavailable, the value for JBmeasured on a 2s2p board in accordance with JMAspecification, JESD51-6, at zero forced air velocity can be used as an alternative, recognizing that this changes the value pr
46、edicted by the resulting model. If JBis indeed used in place of JB, then this should be clearly stated when the two-resistor model is published or disseminated. Note that it is not possible to substitute JTfor JCtop in the creation of the two-resistor model as JTis a thermal characterization paramet
47、er. Thermal characterization parameters are not thermal resistances. This is because when the parameter is measured, the component power is flowing out of the component through multiple paths. JTis often significantly lower than JCtop. For packages which are designed to inject heat directly on to th
48、e ground plane of the board, such as exposed pad packages, the user may consider replacing JBby JCbottom. 6 Application considerations 6.1 Overview The two-resistor model can be used at various stages during the design process. During the initial stage of the design it can be used in back-of-the-env
49、elope calculations to assess the possible bounds of the package behavior. As the design progresses, the model can be used in more detailed simulation tools that either directly support such a model, or provide the basic building blocks from which the model can be built. The simulation tool could belong to either of the following classes: thermal network calculator, three-dimensional simulation tool. It is important to keep in mind that the two-resistor model does not eliminate the need for understanding the applic
