1、JEDEC STANDARD Method for Characterizing the Electromigration Failure Time Distribution of Interconnects Under Constant-Current and Temperature Stress JESD202 MARCH 2006 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed
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10、C Standard No. 202 -i- METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESS Contents 1 Scope 1 2 Significance and Use 1 2.1 Electromigration failure mechanism 1 2.2 Model for electromigration 1 2.3 Test vehicles (Al a
11、nd Cu) 2 2.4 Wafer- and package-level test 2 2.5 Applications 2 2.6 Lower limit on t502 3 Terms and definitions 3 4 Summary of Method 3 4.1 Procedure 3 4.2 Test options 4 4.3 Parameters to be selected 4 5 Precautions and Interferences 5 5.1 Errors in mean current density and temperature stresses 5 5
12、.2 Deviations from the stress means 5 5.3 Thermal interactions 5 5.4 Selecting a percent change in resistance for failure criterion 6 5.5 Excluding test lines 7 5.6 Limit on applied voltage 7 5.7 Recovery from failure 7 5.8 Metallization stability 7 5.9 Lower limit on t507 5.10 Normalization tempera
13、ture 7 5.11 Test line geometry 8 5.12 Low-k dielectrics 8 5.13 Standard probe-pad layout 8 5.14 Temperature range 8 5.15 Convective heat loss 8 5.16 Degradation of thermocouple calibration 8 5.17 Effect of vias on t50and sigma 9 6 Preparatory measurements 9 6.1 Elevated ambient temperature measureme
14、nts 9 6.2 Temperature coefficient of resistance 10 6.3 Cross-sectional area 10 6.4 Stress current 12 6.5 Microscopic inspection 12 JEDEC Standard No. 202 -ii- METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESS Conte
15、nts 6.6 Thermal response time of package 12 6.7 Thermal resistance 13 7 Electrical test system 14 7.1 Stress current control 14 7.2 Display resolution 14 7.3 Maximum applied voltage 14 8 Procedure 15 8.1 Install test parts 15 8.2 Measure the resistance of test lines at the lower temperature 15 8.3 D
16、etermine TCR(TL) of the test lines to be measured 15 8.4 Calculate the stress current through each test structure 16 8.5 Measure test line resistance R(tl)Hat the high ambient stress temperature TH16 8.6 Initiate the stress test 17 8.7 Determine time to failure of each test line 17 8.8 Determine the
17、 mean stress temperature Tmof the test lines 18 8.9 Verify if failure data can be modeled by a single log-Normal distribution 18 9 Analysis of Complete Time to Failure, t, Data 19 9.1 Calculate sample estimates of t50and sigma 19 9.2 Calculate confidence limits of t50and sigma 19 9.3 Calculate a sam
18、ple estimate of tpand its confidence limits 20 10 Analysis of Singly, Right-Censored Time to Failure, tf, Data 21 10.1 Calculate sample estimates of t50and sigma 21 10.2 Calculate approximate confidence limits of t50and sigma 22 10.3 Calculate a sample estimate of tpand its approximate confidence li
19、mits 23 11 Required Reporting 24 11.1 Test structure description 24 11.2 Test option, conditions, and results 24 12 References 24 ANNEX A: Sample Calculations Involved in Sections 9 and 10 26 JEDEC Standard No. 202 Page 1 METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF IN
20、TERCONNECTS UNDER CONSTANT CURRENT-DENSITY AND TEMPERATURE STRESS (From JEDEC Board Ballot JCB-05-59, formulated under the cognizance of the JC-14 Committee on Quality and Reliability of Solid State Products.) 1 Scope This is an accelerated stress test method for determining sample estimates and the
21、ir confidence limits of the median-time-to-failure, sigma, and early percentile of a log-Normal distribution, which are used to characterize the electromigration failure-time distribution of equivalent metal lines subjected to a constant current-density and temperature stress. Failure is defined as
22、some pre-selected fractional increase in the resistance of the line under test. Analysis procedures are provided to analyze complete and singly, right-censored failure-time data. Sample calculations for complete and right-censored data are provided in Annex A. The analyses are not intended for the c
23、ase when the failure distribution cannot be characterized by a single log-Normal distribution. 2 Significance and use 2.1 Electromigration failure mechanism Electromigration is a metallization failure mechanism that leads to excessive increases in resistance or even an open circuit in metallizations
24、. It is important to those who are concerned about the reliability of electrical interconnections in microelectronic circuits and devices. The stress drivers for this failure mechanism are current density and temperature. The method is used to provide failure-time data for: assessing metallization r
25、eliability, making major decisions for the selection of metallization and processing technologies, and monitoring process control. Failure is defined as some fractional increase in the resistance of a test line. 2.2 Model for electromigration The method assumes that Blacks equation 1 (eq. 1) can sat
26、isfactorily model how the sample estimate of the median-time-to-failure, t50s, (from an accelerated electromigration stress test) depends on current density and temperature. The model parameters for temperature and current density are, respectively: the activation energy, Ea, and the value of the ex
27、ponent, n, to which the current density, J, is raised. nasJkTEAt)/(exp50= (1) where: A is a constant; n is a constant; J is the mean current density of the test lines stressed; Eais the activation energy; k is Boltzmanns constant (8.62 10-5eV/K); and T is the mean stress temperature of the test line
28、s stressed. NOTE Experimental determinations of model parameters n and Ea may be obtained by use of JEDEC standard JESD63 2. JEDEC Standard No. 202 Page 2 2 Significance and use (contd) 2.3 Test vehicles (Al and Cu) The test vehicle is a four-terminal, thin-film, metal test line structure where the
29、failure criterion is either an open circuit or a prescribed percent increase in the resistance of the line. Test lines may include contacts and vias to different metallization levels. The metal lines are made of aluminum- or copper-based, thin-film metallizations that are intended for use in microel
30、ectronic circuits and devices. The test line will consist of a primary conductor of aluminum or copper, and usually an adjoining thinner and higher resistivity conductor film. Aluminum metallizations may include a higher-resistivity, adjoining conductor film that can bypass an opening in the primary
31、 conductor due to electromigration. Test lines may have additionally adjacent-running lines that can serve as extrusion monitors. Copper metallizations will generally be of a damascene construction and be enclosed by a thin, higher-resistivity, adjoining copper-diffusion-barrier film. In both cases,
32、 these higher resistivity films are designed to conduct only a small fraction of the current in the undamaged test line. 2.4 Wafer- and package-level test The method allows the test line to be stressed on a heated stage while still part of the wafer (or portion thereof) or stressed in an oven while
33、bonded in a package and electrically accessible via package connections. 2.5 Applications The method is intended for use as a referee method by different testing facilities and for use at testing stations for comparing different metallizations and different processing procedures, and for monitoring
34、product reliability. It can be used as a tool in qualifying vendors and in determining the use-life of a metallization. It can also be used as an instructional instrument to aid first users and to alert the user to potential measurement interferences that could impact the accuracy of the sample esti
35、mates. 2.6 Lower limit on t50The method is normally intended for use under stress levels where the median-time-to-failure, t50, is of the order of hours. Greater stress levels can be used to reduce the test time as long as the time to achieve the stress temperature in the test lines is less than a s
36、mall fraction of t50and no new failure modes or significant material changes are stimulated by the higher stress. JEDEC Standard No. 202 Page 3 3 Terms and definitions 3.1 metallization: A thin-film metallic conductor used to interconnect microcircuit elements. NOTE In addition to the primary, low-r
37、esistivity metal conductor, the metallization may include a thin, higher-resistivity adjoining film. 3.2 test line: A metallization line of specified dimensions, with or without vias making connections to over- or under-lying metal levels, whose length is defined by the location of two voltage taps
38、used to make Kelvin-like resistance measurements of the test line when two other terminals force a current through the line. NOTE It is assumed that the major portion of the test-line length will have a uniform cross-sectional area. 3.3 test structure: A passive metallization structure, including a
39、test line, that is fabricated on a semiconductor wafer by procedures used to manufacture microelectronic integrated devices. 3.4 test chip: A part of a wafer, containing one or more test structures, that is stressed according to the test method either at the wafer level or in a package. 4 Summary of
40、 method 4.1 Procedure The method involves subjecting a sample of N test lines to high current-density and high ambient temperature stress, calculating the mean stress temperature of the test line (which includes any Joule heating) before any significant electromigration damage can occur, and measuri
41、ng the time to failure of each test line, t. A test is performed to determine if the experimentally determined failure times can be modeled by a single log-Normal distribution with the parameters t50(median time to failure) and (sigma). If the test is conducted until all parts on test have failed, s
42、o that the fail time data is complete, then the sample estimate of the median-time-to-failure, t50s, for the stress conditions used in the test, is given by the exponential of the mean of the logarithms of the time-to-failure values: )(lnexp50 meanstt = (2) And, the sample estimate of the sigma of t
43、he distribution, s, is given by the standard deviation of the logarithm of the time-to-fail values: )1()(ln(ln12=NttsNimeani(3) JEDEC Standard No. 202 Page 4 4 Summary of method (contd) 4.1 Procedure (contd) Confidence limits for the sample estimates of t50and s are calculated with the use of the t-
44、distribution and the chi-squared distribution, respectively. The p-th percentile of the fail time distribution, tps, is computed from tps= exp(t50s+ zps), where zpis the p-th percentile of the standard normal distribution. Estimated confidence limits for tpare calculated using the noncentral t-distr
45、ibution. If the test is halted before all parts on test have failed, so that the fail time data is censored, then a method based on the Persson and Rootzen approach is used, which gives closed-form estimators of t50and sigma. Approximate confidence limits for t50, sigma, and tpare developed from the
46、 work of Meeker using the Normal-approximation method. 4.2 Test options Three testing options are included in the test method, each involving somewhat different considerations: Option 1 - The test structures to be stressed are part of either the entire or some portion of a wafer that is placed on a
47、heated stage. The test structures are contacted by individual or a fixed array of probes and are stressed sequentially. This requires the dedication of a wafer-probe station. Option 2 - Each test structure is individually packaged and stressed in a temperature-controlled oven. The thermal response t
48、ime of a packaged test structure is dependent on the size and design of the package and may be of the order of several minutes. Therefore, if Joule heating is significantly large, the measurement of the stress temperature of the test line at the beginning of the test will need to be delayed until th
49、e test line is in thermal equilibrium with its package. Option 3 Adjacent lying test lines on a wafer or in a package are stressed at the same time. Part of the heat path to the stress ambient of each test line is shared by the others. Hence, the test lines communicate thermally with each other during the stress test. For this reason, the option may, in addition, require a calculation of a thermal resistance that is used to calculate the mean stress temperatures of the test lines as each fails and the total power dissipation decreases. 4.3 Parameters to be
