1、 JEDEC STANDARD Serial Interface for Data Converters JESD204C (Revision of JESD204B.01 January 2012) DECEMBER 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors lev
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9、 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 204C -i- SERIAL INTERFACE FOR DATA CONVERTERS CONTENTS Foreword xii 1 Scope . 1 2 Normative references 3 3 Terminology . 4 3.1 Terms and definitio
10、ns 4 3.2 Symbols and abbreviated terms . 9 4 Introduction and common requirements 17 4.1 Application overview 17 4.1.1 Background . 17 4.1.2 Physical layer overview . 18 4.1.3 Transport and link layer overview . 19 4.1.3.1 Data encoding and organization 19 4.1.3.2 Clocking 19 4.1.3.3 Sync header str
11、eam 21 4.1.3.4 Deterministic latency . 21 4.1.4 Data link properties . 21 4.1.4.1 Variants and modes . 22 4.1.5 Configuration examples 22 4.1.5.1 General 22 4.1.5.2 Single-device ADC application . 22 4.1.5.3 Single-device DAC application . 24 4.2 Deterministic latency . 25 4.2.1 Introduction and gen
12、eral requirements 25 4.2.2 No support for deterministic latency (device subclass 0 and device subclass 1 using MULTIREF) 28 4.2.3 Deterministic latency using SYSREF (device subclass 1) 28 4.2.4 Deterministic latency using SYNC detection (device subclass 2) . 28 4.3 Physical timing 29 4.3.1 Device cl
13、ock 29 4.3.2 Link layer clock . 30 4.3.3 Transport layer clock . 30 4.3.4 Local multiframe and extended multiblock clocks (LMFC and LEMC) 31 4.3.5 SYSREF signal (device Subclass 1) 31 4.3.6 MULTIREF signal (device subclass 1) . 33 4.3.7 SYNC generation and detection clocks (8B/10B link layer) . 35 4
14、.3.8 Skew and latency variation budget 36 4.4 Control interfaces 47 4.5 Device classification . 47 4.5.1 Classes . 47 4.5.2 Device subclassification 47 4.5.3 Features to be declared 48 5 Physical layer specification . 49 5.1 Category B physical layer specification 49 5.1.1 Electrical specification o
15、verview 49 5.1.2 Compliance types 50 5.1.3 Transmission medium . 51 5.1.3.1 Transmission medium insertion loss . 52 5.1.4 Class B-3 ( LV-OIF-SxI5) . 52 5.1.4.1 Compliance . 52 5.1.4.2 Transmitter 53 5.1.4.3 Receiver . 54 5.1.5 Class B-6 (LV-OIF-6G-SR) 56 JEDEC Standard No. 204C -ii- SERIAL INTERFACE
16、 FOR DATA CONVERTERS CONTENTS (contd) 5.1.5.1 Compliance . 56 5.1.5.2 Transmitter 57 5.1.5.3 Receiver . 59 5.1.6 Class B-12 (LV-OIF-11G-SR) 60 5.1.6.1 Applicability above 11.1 Gbps 60 5.1.6.2 Compliance . 61 5.1.6.3 Transmitter 62 5.1.6.4 Receiver . 64 5.2 Category C physical layer specification 66
17、5.2.1 Overview . 66 5.2.2 Common transmitter electrical specifications . 68 5.2.3 Common receiver electrical specifications 69 5.2.4 Common JESD204C channel operation margin (JCOM) parameters . 70 5.2.5 Class C-S . 71 5.2.6 Class C-M 72 5.2.7 Class C-R 73 5.2.8 Reference channels 73 5.2.9 Compliance
18、 . 76 5.2.9.1 Transmitter 76 5.2.9.2 Receiver . 76 5.2.9.3 Channel . 77 5.2.9.4 Isolation . 78 5.2.10 Transmitter definitions 79 5.2.10.1 Transmitter test fixture 79 5.2.10.2 Signaling rate and range 81 5.2.10.3 Signaling levels . 81 5.2.10.4 Transmitter transition (rise/fall) time 82 5.2.10.5 Trans
19、mitter output return loss . 83 5.2.10.6 Transmitter output waveform 85 5.2.10.7 Transmitter output noise and distortion . 87 5.2.10.8 Waveform acquisition . 88 5.2.10.9 Test pattern 88 5.2.10.10 Linear fit to the waveform measured at TP0a 88 5.2.10.11 Removal of the transfer function between the tra
20、nsmit function and TP0a . 89 5.2.10.12 Transmitter output jitter . 90 5.2.11 Receiver definitions . 92 5.2.11.1 Receiver test fixture 92 5.2.11.2 Signaling rate and range 94 5.2.11.3 Signaling levels . 95 5.2.11.4 Receiver input return loss 95 5.2.11.5 Receiver sensitivity . 97 5.2.11.6 Receiver jit
21、ter tolerance . 97 5.2.12 JESD204C channel operation margin (JCOM) . 98 5.2.12.1 Link model 98 5.2.12.2 Implementation 100 5.2.12.3 Device class . 100 5.2.12.4 Measurement of the channel 101 5.2.12.5 Coupling 102 5.2.12.6 Transmitter and receiver device package models 102 5.2.12.7 Path terminations
22、. 107 5.2.12.8 Filters. 108 JEDEC Standard No. 204C -iii- SERIAL INTERFACE FOR DATA CONVERTERS CONTENTS (contd) 5.2.12.9 Pulse response . 115 5.2.12.10 Determination of variable equalizer parameters 116 5.2.12.11 Interference and noise amplitude . 118 5.2.12.12 Availability Error! Bookmark not defin
23、ed. 6 Transport layer 121 6.1 Overview . 121 6.2 User data format for an independent lane 121 6.2.1 General 121 6.2.2 User data mapping without oversampling . 122 6.2.3 User data mapping with oversampling 124 6.3 User data format for multiple lanes . 125 6.4 Tail bits 128 6.5 Idle mode . 128 6.5.1 G
24、eneral 128 6.5.2 Dummy Samples . 128 6.6 Test modes 129 6.6.1 General 129 6.6.2 Short transport layer test pattern 129 6.6.3 Long transport layer test pattern 130 7 64B/66B and 64B/80B link layer 131 7.1 Overview . 131 7.1.1 64B/66B and 64B/80B encoding . 131 7.1.2 Block structure 131 7.1.3 Multiblo
25、ck structure 132 7.1.4 Extended multiblock structure . 132 7.1.5 Data channel 132 7.1.6 Sync header stream 132 7.2 Physical coding sublayer . 133 7.2.1 Overview . 133 7.2.2 Transmit process . 133 7.2.3 Receive process . 135 7.2.4 Scrambling and descrambling . 135 7.2.4.1 Overview . 135 7.2.4.2 Scram
26、bler 136 7.2.4.3 Descrambler 136 7.2.5 Fill bits for 64B/80B encoding 137 7.2.6 Gearbox . 138 7.3 Sync header stream . 138 7.3.1 Overview . 138 7.3.2 Sync header encoding and decoding . 138 7.3.3 Pilot signal . 139 7.3.4 CRC-12 signal . 139 7.3.5 CRC-3 signal . 140 7.3.6 FEC signal . 141 7.3.7 Comma
27、nd channel . 142 7.3.7.1 Overview . 142 7.3.7.2 Stand-alone command channel 142 7.3.7.3 Command word encoding . 143 7.3.7.4 Header and payload sequence . 144 7.3.7.5 Operating modes . 145 7.3.7.6 Function codes. 146 JEDEC Standard No. 204C -iv- SERIAL INTERFACE FOR DATA CONVERTERS CONTENTS (contd) 7
28、.4 CRC encoding . 146 7.4.1 General 146 7.4.2 CRC-12 encoding 147 7.4.3 CRC-3 encoding 148 7.5 FEC encoding 149 7.5.1 General 149 7.5.2 FEC encoding 149 7.5.3 FEC decoding 150 7.5.3.1 FEC code reconstruction . 150 7.5.3.2 FEC code decoding . 151 7.6 Receiver Operation 154 7.6.1 Sync header alignment
29、 154 7.6.2 Extended multiblock alignment . 155 7.6.3 Error handling . 157 7.6.3.1 Error kinds . 157 7.6.3.2 Action taken on error . 158 7.6.3.3 Error reporting via control interface 158 8 8B/10B link layer . 159 8.1 8B/10B encoding . 159 8.2 Transmission order 159 8.3 Scrambling 160 8.3.1 Introducti
30、on . 160 8.3.2 Scrambler polynomial . 160 8.3.3 Scrambler bit order 161 8.3.4 Scrambler type . 162 8.3.5 Early synchronization option . 163 8.3.6 Initial state . 164 8.3.7 Scrambling disable 164 8.4 Link operation . 165 8.4.1 Code group synchronization 165 8.4.2 Combination of synchronization reques
31、ts . 167 8.4.3 Initial frame synchronization . 168 8.4.4 Frame alignment monitoring and correction . 168 8.4.4.1 Alignment characters . 168 8.4.4.2 Character replacement without scrambling . 169 8.4.4.3 Character replacement with scrambling 170 8.4.4.4 Frame alignment correction in the RX 171 8.4.5
32、Initial lane alignment . 171 8.4.5.1 General principles . 171 8.4.5.2 Multiframes . 172 8.4.5.3 Initial lane alignment sequence . 172 8.4.6 Lane alignment monitoring and correction . 174 8.4.7 Link re-initialization 175 8.4.8 Test modes 175 8.4.8.1 General 175 8.4.8.2 Test sequences . 176 8.5 Determ
33、inistic latency using SYNC detection (device subclass 2) . 177 8.5.1 Introduction . 177 8.5.2 Accuracy limitations . 177 8.5.3 Principles of SYNC sampling . 179 8.5.3.1 General 179 JEDEC Standard No. 204C -v- SERIAL INTERFACE FOR DATA CONVERTERS CONTENTS (contd) 8.5.3.2 SYNC generation at the RX dev
34、ice . 179 8.5.3.3 Adjustment resolution and adjustment clock . 179 8.5.3.4 Detection resolution at the TX device . 181 8.5.3.5 SYNC de-assertion detection and the detection interval . 181 8.5.4 Master and slave configurations 182 8.5.4.1 Introduction . 182 8.5.4.2 ADC master and slave configurations
35、 . 183 8.5.4.3 DAC master and slave configurations . 184 8.5.5 Summary of requirements for subclass 2 deterministic latency 188 8.6 Receiver operation . 189 8.6.1 Code group synchronization 189 8.6.2 Initial frame synchronization . 191 8.6.3 Initial lane alignment . 193 8.6.4 Monitoring and correcti
36、on of frame and lane alignment . 193 8.6.5 Error handling . 197 8.6.5.1 Error kinds . 197 8.6.5.2 Data output on error 197 8.6.5.3 Errors requiring re-initialization 198 8.6.5.4 Error reporting via the SYNC interface . 198 8.6.5.5 Error reporting via a control interface . 198 8.7 Transmitter operati
37、on 199 8.7.1 Synchronization . 199 8.7.2 Handling of error reports and synchronization requests 201 8.7.2.1 Hard-wired SYNC interface 201 8.7.2.2 Soft SYNC interface 201 8.7.3 SYNC detection in device subclass 2 202 8.8 SYNC interface . 203 8.8.1 Introduction . 203 8.8.2 Hard-wired SYNC interface 20
38、3 8.8.3 Soft SYNC interface 207 8.9 Link configuration parameters and their encoding 207 Annex A (informative) Revision changes 211 The SYNC interface 213 Other substantial changes 213 Device classification and subclassification 214 Annex B (informative) Example of device clock and SYSREF generation
39、 215 Annex C (informative) Background of the values in the skew budget . 217 C.1 Transmission skew 217 C.2 Timing reference skew 218 C.2.1 SYSREF and device clock skew . 218 C.2.2 Device clock and MULTIREF skew . 218 C.2.3 SYNC skew . 219 C.3 Processing skew in logic device 220 C.4 Processing skew i
40、n converter device . 224 C.5 Skew variation . 224 Annex D (normative for compliance) Transmission line model . 225 D.1 Use cases . 225 D.2 Introduction . 225 D.3 Components frequency dependence 226 D.4 Scattering parameters computation . 229 JEDEC Standard No. 204C -vi- SERIAL INTERFACE FOR DATA CON
41、VERTERS CONTENTS (contd) Annex E (informative) Reference JCOM implementation 230 E.1 Invocation 230 E.2 Configuration 230 E.3 Channel data conversion . 235 E.4 Transmitter model . 235 E.5 Receiver model 236 E.5.1 Class C-S reference model 237 E.5.2 Class C-M reference model . 238 E.5.3 Class C-R ref
42、erence model 239 E.6 Model versus silicon correlation . 240 Annex F (normative) JCOM device models interface . 242 F.1 Transmitter 242 F.2 Receiver . 244 Annex G (informative) Conversion of scattering parameters representation . 247 Annex H (normative for category B) Linear insertion loss fit 250 An
43、nex I (normative for category C) Quadratic insertion loss fit 252 I.1 Differential insertion loss 252 I.2 Differential insertion loss deviation 255 Annex J (informative) Physical layer implementation 256 J.1 Transmitter 256 J.2 Receiver . 257 Annex K (normative) Pseudo-random binary sequence (PRBS)
44、generation . 258 Annex L (informative) Transport layer configuration parameters 259 Annex M (informative) Forward error correction decoding 260 M.1 Binary cyclic codes decoding 260 M.2 Shortened cyclic codes decoding . 262 Annex N (informative) Clock Terminology for 64B/66B and 64B/80B link layer .
45、265 Annex O (informative) Clock Terminology for 8B/10B link layer . 266 Annex P (informative) Backward compatibility of 8B/10B link layer with previous versions of JESD204 . 267 Annex Q (informative) Device level implementation for 8B/10B link layer 269 Q.1 TX link layer . 269 Q.2 RX Link Layer 270
46、Annex R (informative) Parallel scrambler and descrambler implementations 271 Annex S (informative) Bibliography . 276 JEDEC Standard No. 204C -vii- SERIAL INTERFACE FOR DATA CONVERTERS CONTENTS (contd) FIGURES Figure 1 JESD204 layer relationship to the IEEE Ethernet model . 12 Figure 2 Scope of orig
47、inal JESD204 and revisions A, B, and C 2 Figure 3 Single device ADC application 23 Figure 4 Single device DAC application 24 Figure 5 Timing diagram illustrating the RX elastic buffer release opportunity in a JESD204C 8B/10B system . 27 Figure 6 SYSREF sampling illustration . 32 Figure 7 SYSREF and
48、MULTIREF signal timing 33 Figure 8 Examples of MULTIREF distribution. Left: multidrop, and right: daisy chain topology. . 34 Figure 9 Illustration of skew items in configuration with multiple ADC devices 37 Figure 10 Illustration of skew items in configuration with multiple DAC devices 38 Figure 11
49、Definition of the skew points on a multi-point ADC link 39 Figure 12 Definition of the skew points on a multi-point DAC link 39 Figure 13 Differential peak-to-peak voltage, 2 . (V high -V low ) 49 Figure 14 Transmission medium differential insertion loss mask. Data rate in Hertz. . 52 Figure 15 Transmit eye mask for class B-3-based operation 54 Figure 16 Line termination at receiver . 55 Figure 17 Receive eye mask for class B-3-based operation . 55 Figure 18 Transmit eye mask for class B-6-based operation 58 Figure 19 Receive eye mask
