1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD205March 2007JEDECSTANDARDFBDIMM Specification:DDR2 SDRAM Fully Buffered DIMM (FBDIMM) Design SpecificationSPECIAL DISCLAIMER: JEDEC has received information that certain patents or patent applications may be relevant to this standard, and, as of the publi
2、cation date of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. http:/www.jedec.org/download/search/FBDIMM/Patents.xls JEDEC does not make any determination as to the validity or relevancy of such patents or patent appl
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8、rd,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the in
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11、EDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 205Page 4Special Disclaimer JEDEC has received information that certain patents or patent applications may be relevant to this standard, and, as of the publication d
12、ate of this standard, no statements regarding an assurance or refusal to license such patents or patent applications have been provided. http:/www.jedec.org/download/search/FBDIMM/Patents.xls JEDEC does not make any determination as to the validity or relevancy of such patents or patent applications
13、. Prospective users of the standard should act accordingly. JEDEC Standard No. 205DDR2 SDRAM Fully Buffered DIMM Design SpecificationRevision 3.0 March 5, 2007 Page 5Product Description 9Product Family Attributes 9Environmental Parameters 10Architecture .11DIMM Connector Pin Description 11DDR2 240-p
14、in FBDIMM Pinout .12Block Diagram: Raw Card Version A (x72 ECC DIMM, one physical rank of x8 DDR2 SDRAMs) 13Block Diagram: Raw Card Version B (x72 ECC DIMMs, two physical ranks of x8 DDR2 SDRAMs) .14Block Diagram: Raw Card Version C (x72 ECC DIMM, one physical rank of x4 DDR2 SDRAMs) 15Block Diagram
15、: RC Versions D,E,H,J (x72 ECC DIMMs, 2 physical ranks of x4 DDR2 SDRAMs) 16Component Details: .17Pin Assignments for x4 and x8 Ballouts without Support Balls .17Pin Assignments for Stacked x4 Ballout without Support Balls .18Pin Assignments for x4 and x8 Ballouts with Support Balls 19Pin Assignment
16、s for Stacked x4 Ballout with Support Balls 20Pin Assignments for x4 and x8 Ballouts with Support Balls 21Pin Assignments for Stacked x4 with Support Balls .22Pin Assignments for x4 and x8 Ballouts with Support Balls 23Pin Assignments for Stacked x4 Ballouts with Support Balls 24Pin Assignments for
17、x4 and x8 PCB Symbol 25Pin Assignments for Stacked x4 PCB Symbol 26Component Details 27Supported SDRAM Component Maximum size for 256Mb to 4Gb, DDR2 SDRAM . 27Architecture .29Advanced Memory Buffer Pin Description 29Pin Assignments for the Advanced Memory Buffer (AMB) .31Critical AMB Specifications
18、. 33DDR2 Fully Buffered DIMM Details 34DDR2 SDRAM Module Configurations (Reference Designs) .34DDR2 Fully Buffered DIMM Design File Releases 34Component Types and Placement 36DDR2 Fully Buffered DIMM Biasing Details 42Common AMB Bias Detail . 42DDR Bias .42DDR VREF BIAS .43PLL and Channel Bias 43Mis
19、cellaneous Bias .44BIAS Components .45DDR2 Fully Buffered DIMM Wiring Details 46Signal Groups . 46JEDEC Standard No. 205DDR2 SDRAM Fully Buffered DIMM Design SpecificationRevision 3.0 March 5, 2007 Page 6General Net Structure Routing Guidelines 46Explanation of Net Structure Diagrams . 47System Cloc
20、k and Data Channel Net Structures 48Recommended Minimum Trace and Shape Separation Rules 51Dual Strip-line Differential Pairs Spacing 52Dual-strip-line Differential Pairs .52Net Structure Routing for AMB Clock Output to SDRAM (Raw Card A) .53Net Structure Routing for AMB Clock Output to SDRAM (Raw C
21、ards B,C) 54Net Structure Routing for AMB Clock Output to SDRAM (Raw Card D) .55Net Structure Routing for AMB Clock Output to SDRAM (Raw Card E, H) 56Net Structure Routing for AMB Clock Output to SDRAM (Raw Card J) 58Net Structure Routing for DQ, CB, DQS, DQS (Raw Cards A, D, J) 59Net Structure Rout
22、ing for DQ, CB, DQS, DQS (Raw Card B) .61Net Structure Routing for DQ, CB, DQS, DQS (Raw Card C) 62Net Structure Routing for DQ, DQS, DQS (Raw Cards E, H; excluding DQS8/17, DQS8/17) .63Net Structure Routing for CB, DQS8/17, DQS8/17 (Raw Cards E, H) 64Net Structure Routing for Address/Command to SDR
23、AM (Raw Card A) 66Net Structure Routing for Address/Command to SDRAM (Raw Cards B, C) .67Net Structure Routing for Address/Command to SDRAM (Raw Cards B, C) .68Net Structure Routing for Address/Command to SDRAM (Raw Card D) 69Net Structure Routing for Address/Command to SDRAM (Raw Cards E, H; exclud
24、ing A4, A7, A10, BA0, BA2 and ODT) .70Net Structure Routing for A4, A7, A10, BA0, BA2, ODT to SDRAM (Raw Cards E, H) 71Net Structure Routing for Address/Command to SDRAM (Raw Card J; excluding ODT) .74Net Structure Routing for ODT to SDRAM (Raw Card D) .75Net Structure Routing for ODT to SDRAM (Raw
25、Card J) 76Net Structure Routing for Control to SDRAM (Raw Cards A, B) .77Net Structure Routing for Control to SDRAM (Raw Cards C) .78Net Structure Routing for Control to SDRAM (Raw Cards D, J) .79Net Structure Routing for Control to SDRAM (Raw Card E; excluding S0L and CKE1R) 80Net Structure Routing
26、 for S0L and CKE1R to SDRAM (Raw Card E) 81Net Structure Routing for Control to SDRAM (Raw Card H; excluding S0L, S1L and CKE1R) 82Net Structure Routing for S0L, S1L and CKE1R to SDRAM (Raw Card H) 83Cross Section Recommendation .84Example Six Layer Stackup 84Example Trace Geometries, Single Ended .
27、85Example Trace Geometries, Differential .85Example Eight Layer Stackup .86Example Ten Layer Stackup 86Example Timing Budget 87Example DIMM Post-AMB Read Timing (PC2-4200/PC2-5300/PC2-6400)1 . 87Example DIMM Post-AMB Write Setup Timing (PC2-4200/PC2-5300/PC2-6400)1 . 87Example DIMM Post-AMB Write Ho
28、ld Timing (PC2-4200/PC2-5300/PC2-6400)1 . 88Example DIMM Post-AMB CK-to-DQS Timing (PC2-4200/PC2-5300/PC2-6400)2 . 88JEDEC Standard No. 205DDR2 SDRAM Fully Buffered DIMM Design SpecificationRevision 3.0 March 5, 2007 Page 7Example DIMM Post-AMB CK-to-C/A/Control Setup Timing (PC2-4200/PC2-5300/PC2-6
29、400)1 88Example DIMM Post-AMB CK-to-C/A/Control Hold Timing (PC2-4200/PC2-5300/PC2-6400)1 89Design collateral for specific Raw Cards 91ODT values . 91Test Mode collateral 93Transparent Mode Pinout 93Recommended trace keepout 95Trace keep out area in connector area .95Trace keep out area in module to
30、p edge area 95Vcc Power Delivery .97Effective Resistance Target 4.75 mOhm Nominal 23C(room temp) 97Kelvin Measurement Ports 97Suggested equipment requirements for measurements 98Rkelvin Measurement Diagram .98VTT Provisions 99Example Complementary CA Bus Current Path .99Example FB-DIMM bridge connec
31、tion requirement 100Effective Resistance (mOhm) Max (room temp) for 533/667 FB-DIMMs 101(Shows typical Left Edge finger to RTTnetwork, use similar ports for right side) 102Typical Rkelvin Ports (Shows example R bridge measurement) .103Serial Presence Detect Definition 105Example 512Mb 1 rank 533 4-4
32、-4 SPD image 105FBDIMM Label Format .110DIMM Mechanical Specifications .112Summary of FB-DIMM Support/Development Hardware 113Diagnostic Sense Line 115General Concept .115Implementation Details .116Capacitor Pad Connection Concept 116Capacitor Connection Pad Size and Placement . 116Capacitor Connect
33、ion Pad 116Diagnostic Sense Line Routing Line Width and Spacing 116Diagnostic Sense Line Same Layer Isolation 116Diagnostic Sense Line Adjacent Layer Isolation . 116Diagnostic Sense Line Reference Planes .117Diagnostic Sense Line Reference Plane Shape and Location 117JEDEC Standard No. 205DDR2 SDRAM
34、 Fully Buffered DIMM Design SpecificationRevision 3.0 March 5, 2007 Page 8Diagnostic Sense Line Layer Change VIA location . 117Routing around the DIMM Key Notch . 118Layer Change Transition VIA Location .118Routing Around the DIMM Key Notch .118Diagnostic Sense Line Topologies, Segment Lengths, and
35、Terminations 118Preferred Topology . 119Diagnostic Sense Line - Preferred Topology 119Alternate Topology (Forked Topology) 119Diagnostic Sense Line - Alternate Topology .120Conclusion .121Revision Log 124JEDEC Standard No. 205DDR2 SDRAM Fully Buffered DIMM Design Specification Product DescriptionRev
36、ision 1.0 May 1, 2006 Page 9Product DescriptionThis specification defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/ PC2-6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).These SDRAM FB-DIMMs are inte
37、nded for use as main memory when installed in systems such as servers and workstations. PC2-4200/PC2-5300/PC2-6400 refers to the DIMM naming convention in which PC2-4200/PC2-5300/PC2-6400 indicates a 240-pin DDR2 DIMM running at 266/333/400 MHz DRAM clock speed and offering 4266/5333/6400 MB/s bandw
38、idth.Reference design examples are included which provide an initial basis for Fully Buffered DIMM designs. Modifications to these reference designs may be required to meet all system timing, signal integrity, and ther-mal requirements for PC2-4200/PC2-5300/PC2-6400 support. All Fully Buffered DIMM
39、implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the designDIMM DRAM DRAM ClockSingle DIMM BandwidthChannel ClockChannel Transfer RatePC2-4200 DDR2-533 266 MHz 4266 MB/s 133 MHz 3.2 GT/sPC2-5300 DDR2-667 333 MHz 5333 MB/s 166 MHz
40、4.0 GT/sPC2-6400DDR2-800 400 MHz 6400 MB/s 200 MHz 4.8 GT/sProduct Family Attributes DIMM organization x72 ECC DIMM dimensions (nominal) 30.35mm (height) x 133.35mm (width) x 8.2 mm (max thickness) MO-256 variation AB30.35mm (height) x 133.35mm (width) x 8.8 mm (max thickness) MO-256 variation BBPin
41、 count 240SDRAMs supported256Mb, 512Mb, 1Gb, 2Gb, 4GbCapacity 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GBSerial PD Consistent with JC 45Supply voltages (nominal)min typ max1.7 1.8 1.9 (DRAM VDD/VDDQ, AMB VDDQ)1.45511.51.5751(AMB VCC/VCCFBD)0.453*VDD0.5*VDD0.547*VDD(DRAM Interface VTT) This supply should
42、track as 0.5 * 1.8 volt supply3.0 3.3 3.6 (VDDSPD)Buffer Interface High-speed Differential Point-to-point Link at 1.5 voltDRAM Interface SSTL_18Note 1: Approximate DC values, refer to AMB Component Specification for actual DC and AC values and conditions. Note 2: Vtt range accomodates measurable off
43、set due to complementary CA bus current paths. (See Vtt section) An Unloaded system should supply Vtt of 0.48*Vdd/0.52*Vdd to Dimm socketJEDEC Standard No. 205DDR2 SDRAM Fully Buffered DIMM Design Specification Product DescriptionRevision 1.0 May 1, 2006 Page 10Environmental RequirementsDDR2 SDRAM F
44、ully Buffered DIMMs are intended for use in standard office environments that have limited capacity for heating and air conditioning. Environmental Parameters The reference designs for the DIMM PCBs are called the “raw cards”, abbreviated R/C. After the designs have been verified in working systems,
45、 the JEDEC JC-45 committee will post registrations of these R/C designs to the JEDEC web site for use by the industry at large.Product Family Raw Card TypesRaw Card DRAM Data Width# of Ranks # of DRAM Z-axis Width x Height (mm)A x8 1 9 planar 133.35 x 30.35Bx 218planar 133.35 x 30.35Cx4 1 18 planar
46、133.35 x 30.35Dx4236stacked / dual die 133.35 x 30.35Explanar 133.35 x 30.35Hx4236planar 133.35 x 30.35Jxstacked / dual die 133.35 x 30.35Symbol Parameter Rating Units NotesTOPROperating temperature See Note 1HOPROperating humidity (relative) 10 to 90 % 2TSTGStorage temperature -50 to +100 C 2HSTGSt
47、orage humidity (without condensation) 5 to 95 % 2PBARBarometric pressure (operating VID1 is VCCvalue: OPEN = 1.5 V, GND = 1.2 V2RESET AMB reset signal 1RFUReserved for Future Use216VCCAMB Core Power and AMB Channel Interface Power (1.5 Volt) 8VDDDRAM Power and AMB DRAM I/O Power (1.8 Volt) 24VTTDRAM
48、 Address/Command/Clock Termination Power (VDD/2) 4VDDSPDSPD Power 1VSSGround 80DNU/M_TestThe DNU/M_Test pin provides an external connection on R/Cs A-D for testingthe margin of Vref which is produced by a voltage divider on the module. Itis not intended to be used in normal system operation and must
49、 not beconnected (DNU) in a system. This test pin may have other features on future card designsand if it does, will be included in this specification at that time.11Total 2401. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibilityJEDEC Standard No. 205Architecture DDR2 SDRAM Fully Buffered DIMM Design SpecificationPage 12 Revision1.0 March 5, 2007.DDR2 240-pin FBDIMM Pinout Pin#FrontSidePin#Bac
