1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD206JANUARY 2007JEDECSTANDARDFBDIMM: Architecture and ProtocolSPECIAL DISCLAIMER: JEDEC has received information that certain patents or patent applications may be relevant to this standard, and, as of the publication date of this standard, no statements re
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11、ilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 Special Disclaimer JEDEC has received information that certain patents or patent applications may be relevant to this standard, and, as of the publication date of this standard, no statements regarding an assurance or refusal to l
12、icense such patents or patent applications have been provided. http:/www.jedec.org/download/search/FBDIMM/Patents.xls JEDEC does not make any determination as to the validity or relevancy of such patents or patent applications. Prospective users of the standard should act accordingly. JEDEC Standard
13、 No. 206FBDIMM Architecture and Protocol-i-Contents1 Document Organization.11.1 List of Terms and Abbreviations 11.2 Revision History.31.3 Related Documents .42 Fully Buffered DIMM Overview .52.1 Memory Channel .52.1.1 Link Widths .52.1.2 Topologies 62.1.3 AMB Addressing.72.1.4 SMBus Interface .82.2
14、 Physical Layer .82.3 Clocking.82.3.1 Clock Distribution92.3.2 Receiver Data Sampling.92.3.3 Voltage Temperature Compensation FIFO.102.3.4 Daisy-Chain Retiming and Data Merge 102.3.5 DRAM Clock Generation 102.3.6 DRAM Data Return.102.4 Host Memory Interface 112.5 Advanced Memory Buffer (AMB).112.6 O
15、ptions 122.6.1 Number of FBD Lanes122.6.2 ECC and non-ECC DIMMs.132.6.3 Variable Read Latency .132.6.4 L0s State 132.6.5 Protocol Variants 133 Channel Initialization153.1 Reset and Inband Control “Signals” 163.1.1 RESET# Signal.173.1.2 Inband Control “Signals”.173.1.3 Inband Reset Event Detector .17
16、3.1.4 Inband Calibrate Event Detector 183.2 Training Sequence Ordered-sets 183.3 Channel Initialization Sequence 193.3.1 Firmware Transition Control .233.3.2 AMB Internal State Variables .233.3.3 Disable State 243.3.4 Training State .263.3.5 Testing State 293.3.6 Polling State .323.3.7 Config State3
17、63.3.8 L0 State 423.3.9 Calibrate State443.3.10 L0s State 463.4 Channel Re-initialization483.4.1 Enter Self Refresh FSM483.4.2 Fast Reset Flow493.5 Hot-add51JEDEC Standard No. 206-ii-3.5.1 Hot-add AMB Reset513.5.2 Hot-add AMB Calibration513.5.3 Hot-add AMB Testing .523.5.4 Hot-add AMB Timing 523.5.5
18、 Hot-Add Reset Flow .523.6 Hot-remove543.7 Hot-replace 544 Channel Protocol . 554.1 Southbound Frames 554.1.1 Normal Southbound Frames 554.1.2 Fail-over Southbound Frames 564.1.3 Southbound Frame Formats.574.2 Southbound Commands614.2.1 Command Delivery Timing .614.2.2 Concurrent Command Delivery Ru
19、les 624.2.3 Command Encoding .634.2.4 DRAM Commands644.2.5 Channel Commands.644.3 Northbound Frames.714.3.1 Northbound CRC Modes 714.3.2 Northbound Idle Frame.714.3.3 Northbound Alert Frame .734.3.4 Northbound Data Frames .754.3.5 Northbound Status Frame 804.4 DRAM Memory Timing 814.4.1 Read Timing
20、.824.4.2 Write Timing .824.4.3 Simultaneous Read and Write Data Transfers .854.4.4 DRAM Bus Segment Restrictions.855 Reliability, Availability and Serviceability .875.1 Overview875.2 Example Error Flows .875.2.1 Command Error Flow .875.2.2 Write Data Error Flow .875.2.3 Read Error Flow .885.3 Overvi
21、ew of Error Protection, Detection, Correction, and Logging885.4 Error Protection and Detection Methods .905.4.1 CRC Logic Used on Normal Southbound Frames905.4.2 Fail-over Southbound Frames 985.4.3 Fail-over Southbound Frame CRCs .1015.4.4 CRC Generation: 14-bit Lane Northbound Data Frame 1045.4.5 1
22、3-bit Lane Northbound Data Frame1075.4.6 12-bit Lane Northbound Data Frame1095.4.7 Write and Read Data ECC Error Protection .1105.5 Southbound Error Handling at the AMB 1105.5.1 Exiting Command Error State.1115.6 Northbound Error Handling at the AMB.1115.7 Northbound Error Handling at the Host .1115
23、.7.1 Read Return Burst Management .1115.7.2 Read Response Data Error Handling .1125.8 Error Logging.112JEDEC Standard No. 206F-iii-5.8.1 Logging of AMB Southbound Events1125.8.2 Logging of Host Northbound Events.1125.9 Error Injection 1125.10 Fail-over Mode Operation1135.10.1 Fail-over Mode Operatio
24、n on Southbound Lanes.1135.10.2 Fail-over Mode Operation on Northbound Lanes .1135.11 AMB Pass-through Functionality .1135.12 Hot Add and Remove 1145.12.1 Hot Add Sequence .1145.12.2 Hot Remove Sequence 1145.12.3 Hot Replace Sequence.1155.13 Memory Initialization1155.14 Thermal Trip Sensor115JEDEC S
25、tandard No. 206FBDIMM Architecture and Protocol-iv-List of Tables1-1 Terms and Definitions 11-2 Revision History . 31-3 Related Documents. 42-4 AMB Addressing 72-5 FBD DIMM Port High-Speed Signal Pin Count (Full 14-bit NB Option). 82-6 Northbound Bit Lane Options 123-7 Channel Initialization Timing
26、Parameters 163-8 Disable State . 253-9 Training Sequence TS0 (Training) 263-10 Training Duration Estimate at DDR2-667 263-11 Training State 283-12 SB to NB Bit Lane Mapping 303-13 Training Sequence TS1 (Testing) 313-14 Testing State . 323-15 NB_Width_Capability Field. 333-16 Training Sequence TS2 (P
27、olling) 333-17 Polling State 343-18 Training Sequence TS3 (Config). 373-19 Protocol Selection Field 373-20 Config State 383-21 NB Channel Width Selection 393-22 SB_Config Field . 403-23 NB_Config Field 403-24 L0 State. 433-25 Calibrate State. 443-26 Recalibrate State . 453-27 L0s State . 473-28 Self
28、 Refresh Entry. 493-29 Fast Reset Duration Estimate for a 12 AMB system 514-30 Common Features of Normal Southbound Frames 564-31 Common Features of Fail-over Southbound Frames 574-32 Southbound Frame Type Encoding 574-33 Command Frame Format 584-34 Command Frame with Data Format . 594-35 Wdata Addr
29、ess Delivery. 594-36 Command+Wdata Frame Format (4-bit Devices) 604-37 Command+Wdata Frame Format (8-bit Devices) 604-38 Command+Wdata Frame Format Non-ECC 8-bit Devices) 614-39 Command Encoding . 634-40 DRAM Command Mapping Examples 644-41 Channel Command Encoding. 654-42 Table 4-13: Per Rank CKE C
30、ommand Bit Positions 674-43 Soft Channel Reset Command Frame Format 68 4-44 Sync Command Frame Format. 704-45 NOP Frame Format. 704-46 First Northbound Idle Frame Format 724-47 Second Northbound Idle Frame Format . 724-48 Third Northbound Idle Frame Format 734-49 Fourth Northbound Idle Frame Format
31、734-50 Alert Frame Replacing Second Idle Frame 754-51 14-bit Northbound Data Frame Format (with 4-bit Devices). 76JEDEC Standard No. 206-v-4-52 13-bit Northbound Data Frame Format (with 8-bit Devices). 774-53 13-bit Northbound Fail-Over Data Frame Format (8 bit Devices). 784-54 12-bit Northbound Dat
32、a Frame Format (with Non-ECC 16-bit Devices) 794-55 Northbound Register Data Frame Format 794-56 Northbound Status Frame Format 804-57 Status Bit Description. 815-58 AMB Responses to Error Conditions . 895-59 Host Responses to Error Conditions. 895-60 Common Features of Normal Southbound Frames 915-
33、61 Southbound Frame with 72 bit Write Data (4-bit Devices) 935-62 Southbound Frame with Three Commands 985-63 Common Features of Fail-over Southbound Frames (with 8-bit Devices). 995-64 Fail-over Southbound Frame With Three Commands 1045-65 14-bit Northbound Data Frame Format (with 4-bit Devices). 1
34、055-66 13-bit Northbound Data Frame Format (with 8-bit Devices). 1085-67 12-bit Northbound Data Frame Format (with 16-bit Devices). 110JEDEC Standard No. 206FBDIMM Architecture and Protocol-vi-List of Figures2-1 FBD Channel Southbound and Northbound Paths 62-2 Sample FBD Channel Topologies 72-3 Cloc
35、k Distribution Block Diagram. 93-4 AMB Initialization Flow Diagram 153-5 In-band Control Signal Detectors . 183-6 Initialization Sequence Flow 203-7 Alternative AMB Discovery Sequence Flows 223-8 Figure 3-5: Bit Lane Fail over Mechanism Example . 423-9 Recalibrate Sequence Flow. 463-10 L0s Sequence
36、Flow. 483-11 Fast Reset Sequence Flow 503-12 Hot-Add Reset Sequence Flow if Failure. 534-13 “A”, “B”, and “C” Command Delivery Timing . 624-14 Idle Frame LFSR Counter Example . 714-15 Basic DRAM Read Data Transfers on FBD (RD) 824-16 FBack-to-back DRAM Read Data Transfers on FBD (RD-RD) 824-17 Basic
37、 DRAM Write Data Transfers on FBD (WR) 834-18 Write FIFO Minimum Fall Through Time . 844-19 Write FIFO Maximum Fall Through Time 844-20 Write FIFO Maximum Pipelining of Writes for a Single DIMM 854-21 Simultaneous Read and Write Data Transfers on FBD (RD-WR-RD) 85JEDEC Standard No. 206Page 1FBDIMM:
38、Architecture and Protocol(From JEDEC Board Ballot, JCB-06-49, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 Document OrganizationThe next four chapters of the FBD Channel Specification cover Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chap
39、ter 4) and Reliability, Availability, and Serviceability (RAS) (Chapter 5).1.1 List of Terms and AbbreviationsThis document uses the following terms and abbreviations:Note that the terms chipset and memory controller are used interchangeably throughout the rest of this document. The term motherboard
40、 is used as a generic term to describe the PCB onto which the memory controller is mounted. Actual implementations could have distributed memory controllers mounted on separate memory boards.Table 1-1 Terms and DefinitionsTERM DefinitionAMB Advanced Memory BufferChip disable An ECC encoding specific
41、ally tailored for memory such that the data from any defective memory device can be reconstructed from some aggregate of surviving memory devices. Corrects data from failed device.Bit Lane A differential pair of signals in one direction.D+ and D- The D+ and D- terms used in this document are used to
42、 indicate the two conductors or signals of a differential signaling pair.DDR Double Data Rate (SDRAM)DDR Branch The minimum aggregation of DDR channels which operate in lock-step to support error correction. Two channels per branch supports x8 chip disable ECC. A rank spans a branch.DDR Channel A DD
43、R channel consists of a data channel with 72 bits of data and an addr/cntrl channelDDR Data channel A DDR data channel consists of 72 bits of data, divided into 18 data groupsDDR Data group Each data group consists of 4 data signals and a differential strobe pairDIMM Dual In-Line Memory Module. A pa
44、ckaging arrangement of memory devices on a socketable substrate.DIMM Slot Receptacle (socket) for a DIMM. Also, the relative physical location of a specific DIMM on a DDR Channel.DIMM Stack Dual-ranked x4 DRAM DIMM physical topology: refers to two physical rows of DRAM “stacked” one above anotherDRA
45、M Page (Row) The DRAM cells selected by the Row AddressDPM Defects per millionDRAM Dynamic Random Access MemoryECC Error Correction Code.EMI Electro-magnetic interferenceFBD Fully Buffered DIMMJEDEC Standard No. 206Page 2Frame Group of bits containing commands or dataHCSL High-speed Current Steering
46、 LogicHost Memory controller agent on an FBD channelISI Inter Symbol InterferenceJEDEC JEDEC Solid State Technology Association (once known as the Joint Electron Device Engineering Council)JESD79 JEDEC Standard 79, DDR SDRAM SpecificationLink A dual-simplex communications path between two components
47、. The collection of two Ports and their interconnecting bit lanes.Mesochronous Same frequency with unknown (but fixed) phase relation.NB NorthboundNorthbound The direction of signals running from the farthest DIMM toward the host.Page Replace a.k.a. Page Miss, Row Hit / Page MissAn access to a row t
48、hat has another page open. The page must be transferred back from the sense amps to the array, and the bank must be pre-charged.Page Hit An access to an open page, or DRAM row. The data can be supplied from the sense amps at low latency.Page Miss (Empty Page) An access to a page that is not buffered
49、 in sense amps and must be fetched from DRAM array.PLL Phase Locked LoopPort In physical terms, a group of transmitters and receivers physically located on the same chip that define one end of a Link.PTH Plated Through-HolePVT Process, Voltage and TemperatureRank A DIMM is organized as one or two physical sets of memory, called ranks. Note that single rank or dual rank is different from single-sided or double-sided, e.g. a single rank DIMM build from x4 DRAM devices is actually double-sided. It is also common practice to distribute the 9 devices of an x8 DIMM between both side
